Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, first and second electrodes, a gate electrode, a gate terminal, a first conductive member, a first terminal, and a first insulating member. The semiconductor member includes first and second semiconductor regions, and a third semiconductor region provided between the first and second semiconductor regions. The first electrode is electrically connected to the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The gate terminal is electrically connected to the gate electrode. The first conductive member is electrically insulated from the first and second electrodes, and the gate electrode. The first terminal is electrically connected to the first conductive member.

Abstract: A method of manufacturing a nitride semiconductor light-emitting element configured to emit deep ultraviolet light includes: providing a semiconductor structure comprising: an n-side semiconductor layer comprising an n-side contact layer comprising aluminum, gallium, and nitrogen, a p-side semiconductor layer, and an active layer between the n-side semiconductor layer and the p-side semiconductor layer; forming an n-side electrode, which comprises forming, successively from an n-side contact layer side: a first layer located above the n-side contact layer and comprising a titanium layer, a second layer located above the first layer and comprising a silicon-containing aluminum alloy layer, and a third layer located above the second layer and comprising a tantalum layer and/or a tungsten layer; and heating the n-side electrode.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a fin heat-dissipation region on a substrate; a fin channel part on the fin heat-dissipation region, and an isolation structure on the substrate. A width of the fin channel part is smaller than a width of the fin heat-dissipation region. A top surface of the isolation structure is coplanar with a top surface of the fin heat-dissipation region.

Abstract: A MEMS device can include a solid dielectric including a plurality of apertures, the solid dielectric having a first side and a second side. The MEMS device can include a first plurality of electrodes extending completely through a first subset of the plurality of apertures, a second plurality of electrodes extending partially through a second subset of the plurality of apertures, a third plurality of electrodes extending partially into a third subset of the plurality of apertures. The MEMS device can include a first diaphragm coupled to the first plurality and to the third plurality of electrodes, the first diaphragm facing the first side of the solid dielectric. The MEMS device can include a second diaphragm coupled to the first plurality and to the second plurality of electrodes the second diaphragm facing the second side of the solid dielectric.

Abstract: An exemplary embodiment provides an organic light emitting diode display including a substrate, a bridge electrode disposed on the substrate, a buffer layer which covers the bridge electrode, a semiconductor layer disposed on the buffer layer, a first gate insulating layer which covers the semiconductor layer in a plan view, a first gate conductor disposed on the first gate insulating layer and which includes a first gate electrode, a second gate insulating layer which covers the first gate conductor, a second gate conductor disposed on the second gate insulating layer, an interlayer-insulating layer which covers the second gate conductor, and a data line disposed on the interlayer-insulating layer. The first gate electrode is directly connected to the bridge electrode, the semiconductor layer is electrically connected to the bridge electrode, and a capacitance exists between the data line and the bridge electrode.

Abstract: According to one embodiment, a resistive random access memory device includes a first electrode and a second electrode. The resistive random access memory device also includes a resistance change layer connected between the first electrode and the second electrode. The resistive random access memory device also includes a conductive layer connected in series to the resistance change layer between the first electrode and the second electrode. The resistive random access memory device in which the conductive layer includes a plurality of first material layers including a first material and a plurality of second material layers including a second material which is different from the first material.

Abstract: A cross-bar ReRAM comprising a substrate, a plurality of first columns extending parallel to each other on the top surface of the substrate, wherein each of the plurality of the first columns includes a resistive random-access memory (ReRAM) stack comprised of a plurality of layers. A plurality of second columns extending parallel to each other and the plurality of second columns extending perpendicular to the plurality of first columns, wherein the plurality of second columns is located on top of the plurality of first columns, such that the plurality of second columns crosses over the plurality of first columns. A dielectric layer filling in the space between the plurality of first columns and the plurality of second columns, wherein the dielectric layer is in direct contact with a sidewall of each of the plurality layers of the ReRAM stack.

Abstract: A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.

Abstract: A first solid-state imaging element according to an embodiment of the present disclosure includes a bottom-electrode; a top-electrode opposed to the bottom-electrode; a photoelectric conversion layer provided between the bottom-electrode and the top-electrode and including a first organic semiconductor material; and an upper inter-layer provided between the top-electrode and the photoelectric conversion layer, and including a second organic semiconductor material having a halogen atom in a molecule at a concentration in a range from 0 volume % or more to less than 0.05 volume %.

Abstract: A semiconductor device includes first and second semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins respectively includes a first channel region and a second channel region, which the first and second gate structures are respectively on. The first gate structure includes a first silicon oxide layer on the first channel region, a first high-k dielectric layer on the first silicon oxide layer, and a first metal gate on the first high-k dielectric layer. The second gate structure includes a second silicon oxide layer on the second channel region, a second high-k dielectric layer on the second silicon oxide layer, and a second metal gate on the second high-k dielectric layer. The first silicon oxide layer has a Si4+ ion concentration greater than a Si4+ ion concentration of a bottom portion of the second silicon oxide layer.

Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a well region in a substrate and forming an anti-punch through region in a top portion of the well region. The method further includes forming a barrier layer over the anti-punch through region and alternately stacking first semiconductor material layers and second semiconductor material layers over the barrier layer. The method further includes patterning the first semiconductor material layers, the second semiconductor material layers, the barrier layer, and the anti-punch through region to form a fin and removing the first semiconductor material layers and the barrier layer to expose the anti-punch through region. The method further includes forming a gate wrapping around the second semiconductor material layers.

Abstract: A method may include providing a device structure in the semiconductor device. The device structure may include a buried device contact, a first dielectric layer, disposed over the buried device contact; and a device element, where the device element includes a TiN layer. The method may include implanting an ion species into the TiN layer, wherein the ion species comprises a seed material for selective tungsten deposition.

Abstract: A semiconductor device includes at least one active pattern on a substrate, at least one gate electrode intersecting the at least one active pattern, source/drain regions on the at least one active pattern, the source/drain regions being on opposite sides of the at least one gate electrode, and a barrier layer between at least one of the source/drain regions and the at least one active pattern, the barrier layer being at least on bottoms of the source/drain regions and including oxygen.

Abstract: Mobile phones and other mobile devices communicate wirelessly by transmitting and receiving RF signals. Transmitters and receivers in wireless devices process RF signals in certain frequency ranges or bands. Signals in other frequencies can be blocked or filtered out by, for example, a lumped-element circuit or a lumped-element filter consisting of passive electrical components such as inductors, capacitors, and resistors. A passive component device, or integrated passive device, is one example of a lumped-element filter fabricated with passive components on a die. In a mobile device, a passive component device and one or more integrated circuits or other chips used for signal processing are interconnected by being mounted on (i.e., coupled to) a metallization structure or package substrate in a chip module or multi-chip module. The demand for miniaturization of hand-held mobile devices drives a need for reducing the sizes of chip modules that are inside a mobile device.

Abstract: According to one embodiment, a display device including an insulating substrate, a first gate driver, a first gate line and a conductive material layer is provided. The first gate line has a first end connected to the first gate driver and a second end opposite to the first end, and extends in a first direction. The conductive material layer is located between the insulating substrate and the first gate line, overlaps the first gate line, and extends in the first direction. In the display device, the second end of the first gate line is electrically connected to the conductive material layer.

Abstract: In a general aspect, a semiconductor device can include a semiconductor region, an active region disposed in the semiconductor region, and a termination region disposed on the semiconductor region and adjacent to the active region. The termination region can include a trench having a conductive material disposed therein. The termination region can further include a first cavity separating the trench from the semiconductor region. A portion of the first cavity can be disposed between a bottom of the trench and the semiconductor region. The termination region can also include a second cavity separating the trench from the semiconductor region.

Abstract: A white light emitting device may include a substrate, first LEDs disposed on the substrate, a first photoluminescence material disposed over the first LEDs, second LEDs disposed on the substrate, where the first LEDs and the second LEDs emit blue light at substantially the same wavelength, a second photoluminescence material disposed over the second LEDs, the second photoluminescence material having a composition different from the first photoluminescence material, where an emission product of the white light emitting device is a combination of light emitted from (i) a combination of the first LEDs and the first photoluminescence material, and (ii) a combination of the second LEDs and the second photoluminescence material, and a dimming control connected to the first LEDs and to the second LEDs; where the dimming control is actuable to modify the emission product.

Abstract: A semiconductor device includes a gate structure extending from a first surface of a semiconductor portion into a mesa section between neighboring field electrode structures and an alignment layer formed on the first surface. The alignment layer includes mask pits formed in the alignment layer in a vertical projection of the field electrode structures. Sidewalls of the mask pits have a smaller tilt angle with respect to the first surface than sidewalls of the field electrode structures. The gate structure is in the vertical projection of a gap between neighboring mask pits.

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.