Abstract: A light-emitting device includes a substrate comprising a base member, a first wiring, a second wiring, and a via hole; at least one light-emitting element electrically connected to and disposed on the first wiring; and a covering member having light reflectivity and covering a lateral surface of the light-emitting element and a front surface of the substrate. The base member defines a plurality of depressed portions separated from the via hole in a front view and opening on a back surface and a bottom surface of the base member. The substrate includes a third wiring covering at least one of inner walls of the plurality of depressed portions and electrically connected to the second wiring. A depth of each of the plurality of depressed portions defined from the back surface toward the front surface is larger on a bottom surface side than on an upper surface side of the base member.

Abstract: A memory cell design is disclosed. In an embodiment, the memory cell structure includes at least one memory bit layer stacked between top and bottom electrodes. The memory bit layer provides a storage element for a corresponding memory cell. One or more additional conductive layers may be included between the memory bit layer and either, or both, of the top or bottom electrodes to provide a better ohmic contact. In any case, a dielectric liner structure is provided on sidewalls of the memory bit layer. The liner structure includes a dielectric layer, and may also include a second dielectric layer on a first dielectric layer. Either or both first dielectric layer or second dielectric layer comprises a high-k dielectric material. As will be appreciated, the dielectric liner structure effectively protects the memory bit layer from lateral erosion and contamination during the etching of subsequent layers beneath the memory bit layer.

Abstract: A flexible display device includes a substrate, a light emitting layer, a first insulating layer, and a conductive layer. The substrate includes a bent region and a non-bent region. The light emitting layer overlaps the non-bent region. The first insulating layer is disposed on the substrate. The conductive layer is disposed on the first insulating layer. A sidewall of the first insulating layer includes a first tapered surface. The first tapered surface includes at least three curved surface portions continuously arranged with one another.

Abstract: A method of forming an ultrasonic transducer device includes bonding a membrane to seal a transducer cavity with at least a portion of a getter material layer being exposed, the getter material layer comprising a portion of a bilayer stack compatible for use in damascene processing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: Embodiments herein describe techniques for an optical device including a substrate of a wafer. An image sensor device is formed on a front side of the substrate, while a plurality of posts of a metasurface lens are formed on a backside opposite to the front side of the substrate. A post of the plurality of posts includes a metasurface material that is transparent to light. Other embodiments may be described and/or claimed.

Abstract: A method of manufacturing a semiconductor device, including preparing a semiconductor wafer having first and second main surfaces opposite to each other, forming a photoresist film on the first main surface of the semiconductor wafer, forming a plurality of openings at predetermined positions in the photoresist film, cleaning the semiconductor wafer with water after the openings are formed, drying the semiconductor wafer by rotating the semiconductor wafer around a center axis that is orthogonal to the first main surface of the semiconductor wafer, to thereby generate a centrifugal force to cause the water that is left in the openings of the photoresist film to fly off the semiconductor wafer, and ion-implanting a predetermined impurity by a predetermined acceleration energy from the first main surface of the semiconductor wafer, using the photoresist film as a mask, after the drying. The drying process includes setting a rotational speed of the semiconductor wafer to be at most an upper limit value.

Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.

Abstract: Disclosed is a magnetic memory device including a first magnetic pattern that extends in a first direction and has a magnetization direction fixed in one direction, and a plurality of second magnetic patterns that extend across the first magnetic pattern. The second magnetic patterns extend in a second direction intersecting the first direction and are spaced apart from each other in the first direction. Each of the second magnetic patterns includes a plurality of magnetic domains that are spaced apart from each other in the second direction.

Abstract: A layer of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride and the mixed crystals thereof has an upper surface and a bottom surface. The upper surface of a crystal layer of the group 13 nitride includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part, observed by cathode luminescence. The high-luminance light-emitting part includes a portion extending along an m-plane of the crystal of the group 13 nitride. The crystal of the nitride of the group 13 element contains oxygen atoms in a content of 1×1018 atom/cm3 or less, silicon atoms, manganese atoms, carbon atoms, magnesium atoms and calcium atoms in contents of 1×1017 atom/cm3 or less, chromium atoms in a content of 1×1016 atom/cm3 or less and chlorine atoms in a content of 1×1015 atom/cm3 or less.

Abstract: A piezo-junction device may be provided. The piezo-junction device comprises a piezoelectric element comprising two electrodes and piezoelectric material in-between, and a semiconductor junction device adjacent to the piezoelectric element such that one of the two electrodes of the piezoelectric element is in contact with the semiconductor junction device connecting the semiconductor junction device and the piezoelectric element electrically in series. Thereby, the semiconductor junction device and the piezoelectric element are together positioned in a fixed mechanical clamp such that the piezoelectric element with an applied electrical field applies strain to the semiconductor junction device causing a change in Fermi levels of the semiconductor junction device.

Abstract: A sensor can comprise a sensor die with a first sensor surface and a second sensor surface opposite to the first sensor surface. The sensor can further comprise a die pad component with a first pad surface and a second pad surface opposite to the first pad surface, wherein the sensor die is vertically stacked with the die pad component, with the second sensor surface oriented toward the first pad surface. The sensor can further comprise a lead frame component with a first frame surface and a second frame surface opposite to the first frame surface, the die pad component is vertically stacked with the lead frame component, wherein the second pad surface is oriented toward the first frame surface, the second pad surface is isolated from the second frame surface, and the lead frame component is electrically connected to the sensor die.

Abstract: The disclosure provides an electronic device and a method of manufacturing an electronic device. The electronic device includes a first substrate, a plurality of light-emitting dies, a transparent material layer, a sealing material, and a second substrate. The plurality of light-emitting dies are disposed on the first substrate. The transparent material layer is disposed on the first substrate. The sealing material is disposed on the first substrate and surrounds the transparent material layer. The second substrate is adhered to the first substrate through the transparent material layer and the sealing material.

Abstract: An integrated circuit includes gate-all-around (GAA) nanowire transistors, GAA nanosheet transistors, and planar devices on the same substrate. Gate dielectric layers of the GAA nanowire transistors and the GAA nanosheet transistors have substantially the same thickness which is smaller than the thickness of the gate dielectric layer of the planar devices. The channel width of the planar devices is greater than the channel width of the GAA nanosheet transistors, which is greater than the channel width of the GAA nanowire transistors.

Abstract: First p+-type regions are provided directly beneath trenches, separate from a p-type base region and facing bottoms of the trenches in a depth direction. The first p+-type regions are exposed at the bottoms of the trenches and are in contact with a gate insulating film at the bottoms of the trenches. Second p+-type regions are each provided between (mesa region) adjacent trenches, separate from the first p+-type regions and the trenches. Drain-side edges of the second p+-type regions are positioned closer to a source side than are drain-side edges of the first p+-type regions. In each mesa region, an n+-type region is provided separate from the first p+-type regions and the trenches. The n+-type regions are adjacent to and face the second p+-type regions in the depth direction.

Abstract: An implementation of a MEMS device includes a constrained diaphragm comprising a surface, the diaphragm having a net compressive stress; and a backplate comprising a surface facing the surface of the diaphragm, the surface of the backplate having a center, and a post extending from the surface of the backplate, wherein the post is located at or near a center of the surface and limits a maximum deflection of the diaphragm.

Abstract: A MEMS device can include a first support layer, a second support layer, and a solid dielectric suspended between the first support layer and the second support layer. The solid dielectric can move relative to the first support layer and the second support layer and can include a plurality of apertures. The MEMS device can include a first plurality of electrodes coupled to the first support layer and the second support layer and extending through a first subset of the plurality of apertures. The MEMS device can include a second plurality of electrodes coupled to the first support layer and extending partially into a second subset of the plurality of apertures. The MEMS device can include a third plurality of electrodes coupled to the second support layer and extending partially into a third subset of the plurality of apertures.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate a substrate, a first electrode structure on the substrate, the first electrode structure including first insulating patterns and first electrode patterns, the first insulating patterns alternately stacked with the first electrode patterns, a second electrode pattern on a sidewall of the first electrode structure, and a data storage film on a sidewall of the second electrode pattern. The data storage film has a variable resistance.