Abstract: Method for determining at least one optimal trajectory between a point and a target situated in a medium and forming a centered volume, the position of each of whose points is known with geometrical uncertainties, characterized in that it consists in defining for the centered volume a gain which takes different values from the center to the peripheral boundary, and a zero value outside the centered volume; in determining a statistically significant number of instances of the positions of the centered volume as a function of the geometrical uncertainties which affect it, and in determining an aggregate gain at each point; in defining a volume of interest, site of the points with positive aggregate gains in the medium; in defining curvilinear trajectories between at least one entry point and at least one exit point of the said volume of interest; in integrating the aggregate gain along each of the said curvilinear trajectories in such a way as to obtain a profit associated with each trajectory, and in retaining

Abstract: A method of analyzing a circuit having a structural loop between different channel connected components within the circuit first splits the circuit into its constituent channel connected components (100). The structural loops are then detected and broken (101) before obtaining a pair of boolean functions at each break point (102) by inserting a pair of temporary boolean variables at the break point on a boundary between different channel connected components and analyzing each channel connected component in the structural loop utilizing the pair of temporary boolean variables to obtain the pair of boolean functions representing the functionality of the circuit at the break point. The pair of boolean functions are then analyzed (103) to determine whether the structural loop is sequential in nature, and, if so, the pair of boolean functions is modified (105) in order to remove any dependence in the pair of boolean functions on the pair of boolean variables.

Abstract: An algorithim for modeling the interaction of two colliding rigid objects. The algorithm allows the search of the optimal position and stabilization of two rigid objects when they are in contact due to a force pushing them against each other. The method does use mathematical integration and does not use any initial acceleration or speed conditioning for the results. The pushing direction can be changed at any time of the search for a correct specification. The moving solid is translated and rotated incrementally toward the equilibrium position and orientation in a non-natural way but leading to the same final attitude in a large range of initial conditions. One important novelty of this algorithm is the modeling of rotations involved for the moving object to go toward the natural position and orientation it should adopt. This can be done by the detection of torque during the search and the determination of the center of rotation in a quadratic time.

Abstract: It is an object of the present invention to provide a scheme for distributing spatial information between information providers and information users. To achieve this object, the present invention creates a corresponding index for each spatial information. The index includes information related to a position included in spatial information, and data related to a storage location of the spatial information. This index also includes (1) a source ID for uniquely identifying spatial information; (2) coordinate translation values which are parameters used to correspond certain spatial information to other spatial information; and (3) when the spatial information including this index was created by referencing other spatial information, an underlay diagram specifying ID represented by the source ID possessed by the referenced spatial information, or the like.

Abstract: A method and apparatus are provided that reduce the training time associated with machine learning systems whose training time is proportional to the number of outputs being trained. Under embodiments of the invention, the number of outputs to be trained is reduced by dividing the objects to be modeled into classes. This produces at least two sets of model parameters. At least one set describes some aspect of the classes given some context, and at least one other set of parameters describes some aspect of the objects given a class and the context. Thus, instead of training a system with a large number of outputs, corresponding to all of the objects, the present invention trains at least two models, each of which has a much smaller number of outputs.

Abstract: A method for exploring the behavior of a design model, the method including the steps of providing a design model represented as a Finite State Machine (FSM). The method further includes the step of providing a path specification of interest. The method further includes the step of exploring the behavior of the design in order to find and present a scenario in the design that meets the path specification.

Abstract: A technique for translating design test bench generated signals into an Automated-Test-Equipment compatible format using existing digital pattern conversion tools. The technique uses sigma-delta modulation technology to allow conversion of analog and mixed signal stimuli into digital representations that can be converted for use in the target tester using existing digital pattern conversion tools.

Abstract: A method for determining test coverage of an original high level language description which represents an electrical circuit by the data of at least one dump file exported by a simulation program, the original high level description having at least one executable assignment statement which models the circuit, the at least one executable assignment statement having a left side and a right side separated by an assignment operator, the left side being a variable, and the right side being an expression which has a set of at least one variable and at least one logic operator, the expression on the right side, when evaluated, determining a value to be assigned to the variable on the left side, the data of the dump file consisting of the values of all the variables of the originals high level language description between a simulation start time instant and a simulation end time instant the method comprising: a description importing step for importing the original high level language description to form a design data

Abstract: A semiconductor test system which generates a test pattern produced based on data resultant to device logic simulation performed on a computer for an LSI device designed in an electronic design automation (EDA) environment, tests the LSI device, and feedbacks the test results to the EDA environment. The semiconductor test system includes an event file for storing event data obtained by executing device logic simulation in a design stage of an LSI device under test; an event memory for storing the event data from the event file relative to timings; means for generating a test pattern by directly using the event data from the event memory and applying the test pattern to the LSI device under test; a result data file for evaluating a response output of the LSI device under test and storing resultant evaluation data; and means for evaluating design of the LSI device based on the data stored in the result data file.

Abstract: A method for designing and mapping a power-bus grid in an integrated circuit. A floor plan is created by mapping wire segments of the power-bus grid to various metal layers of the IC core. Power zones which specify the current consumption of analog, digital, and memory block regions are also mapped to the IC core. A netlist of the floor plan design is generated and simulated, with the simulation returning current density and a voltage drop values in the wire segments with respect to the power zones. Calculated current density and voltage drop values are analyzed using a color map to indicate the current density and voltage drop levels of the wire segments. Power-bus wire segments are displayed in colors matched to the current density and voltage drop levels in the color map, helping the designer identify potential electromigration and voltage drop problems. The floor plan design can be modified if the calculated density and voltage drop values indicate potential electromigration or voltage drop problems.

Abstract: A method to be used during a product development procedure wherein the procedure includes a series of consecutive development phases and the product includes at least two critical to quality characteristics (CTQs). The method is for generating a confidence matrix which can be used to increase a product sigma through product design. A user initially provides product limits and thereafter provides additional development information during each consecutive development phase. During at least two of the development phases and for each CTQ, development information is used to determine a quality factor which is indicative of the probability that the product will be within the specified limits. Also, for each CTQ, a confidence factor is identified which is indicative of the probability that the quality factor is accurate. Then, quality factors, CTQs and confidence factors are arranged such that the CTQs and factors are correlated.

Abstract: A system and method for testing the quality of a simulation model for the DUT (device under test) through temporal coverage of the testing and verification process. Temporal coverage examines the behavior of selected variables over time, according to a triggering event. Such a triggering event could be determined according to predefined sampling times and/or according to the behavior of another variable, for example. This information is collected during the testing/verification process, and is then analyzed in order to determine the behavior of these variables, as well as the quality of the simulation model for the DUT. For example, the temporal coverage information can be analyzed to search for a coverage hole, indicated by the absence of a particular value from a family of values.

Abstract: Bayesian principal component analysis. In one embodiment, a computer-implemented method for performing Bayesian PCA including inputting a data model; receiving a prior distribution of the data model; determining a posterior distribution; generating output data based on the posterior distribution (such as, a data model, a plurality of principal components, and/or a distribution); and, outputting the output data. In another embodiment, a computer-implemented method including inputting a mixture of a plurality of data spaces; determining a maximum number of principal components for each of the data spaces within the mixture; and, outputting the maximum number of principal components for each of the data spaces within the mixture.

Abstract: A circuit simulator is provided for simulating the operation of a circuit in the time domain by accounting for the physical fluctuation (noise) in the time domain. Each of the components (14) in the matrix (10) has associated therewith an active current generator which can be simulated by the simulator in the time domain. In parallel with this active current generator, a stochastic (random) process current generator is provided. This stochastic current generator for each element will utilize a Gaussian random number generator (with 0 mean and a variance equal to 1) that is scaled by the standard deviation (square root of the variance) of the physical noise process that exists within the device. Additionally, this Gaussian random number generator is scaled by a factor that accounts for the time step or discrete operation of the noise simulator.

Abstract: A method and an apparatus make available uncommitted register values during the random code generation process. When there is a need for a register to contain a specific (desirable) value, then the register value is committed to that value at that point. Uncommitted values can propagate through one or more previous instructions. All registers and memory begin the test program in the uncommitted state. When the random code generators is done generating the test program, if any uncommitted values remain, then the uncommitted values are committed to arbitrary values.

Abstract: An integrated circuit, apparatus and method is provided for programming manufacturing information and software program information upon non-volatile storage elements on the integrated circuit. The manufacturing information includes information as to a specific processing recipe or layout used to form hardware of the integrated circuit. The software information indicates a specific revision of software used to program the integrated circuit, or a programming tool used to input the software into the integrated circuit. Combination of software and hardware is therefore embodied in non-volatile storage elements as product engineering bits. The product engineering bits can be called upon and read by the manufacturer or by the customer outside normal operation of the integrated circuit. A comparison of the hardware and software revisions will indicate possible incompatibility.

Abstract: Methods and apparatuses are provided for modeling the compensation error and simulating registration error of a multilayer printed circuit board. Experiments are conducted in order to model compensation error which factor one or a combination of the following: the dielectric layer, the position of the core in the stack, the circuit configuration, the assembly of the printed circuit board, and the interaction between the core and the dielectric layer. The registration simulator combines the sources of registration error in an interdependent manner so as to model overall registration error over the panel surface.

Abstract: A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program is executed on the multiprocessor computer to determine the number of current processors in the multiprocessor computer and the revision number of each processor. A software program that compares the revision numbers of the current processors with processor compatibility information is then executed to determine the revision numbers of processors that are compatible with all current processors.

Abstract: First, a graph of a set of transition sequences representing the property to be satisfied by a finite state machine which is a model of a logical device. Then, a node to be processed is selected from the graph, and one of the branches connected to the node is selected. A mapping operation is performed on a set of states of the node on the starting side of the selected branch, and the result is added to the set of states of the node on the ending side. As a result of the mapping operation, it is determined whether or not the set of states which satisfies the target property has been obtained, that is, whether or not an example of a transition sequence has been successfully detected. If it has been successfully detected, then it is assumed that there is a transition sequence, the process terminates. If it has not been successfully detected, then it is determined whether or not there is an unprocessed branch connected to the node. If yes, the above described process is repeated.

Abstract: The present invention is directed to a simulation testbench 10 which includes a circuit under test 14 and a plurality of test models 12 designated 1 through N. The test models 12 include at least one of a driver and a monitor. The drivers selectively apply stimuli to the circuit under test 14, and the monitors observe responses to the stimuli from the circuit under test 14. A single controller 16 is provided for the plurality of test models 12. The controller 16 has an instruction source 18 including a list of commands which control the plurality of test models 12. The commands are routed from the instruction source 18 over a model control bus 24 to the plurality of test models 12.