Abstract: A method for checking on cyclicity of a set of definitions employs a simple, non-computational definition of constructivity and a symbolic algorithm based on the new, simple to implement, formulation for variables with arbitrary finite types. This is accomplished by extending variable type to include the “undeterminable” value ⊥ (read as “bottom”). This formulation is non-computational and easily extensible to variables with any finite type. The formulation also handles definitions of indexed variables in the same manner. The set of definitions is then checked to determine whether any of the variables assume the value is ⊥.

Abstract: A block dividing means (2) receives an original netlist (D1) defining a circuit to be simulated, selects a to-be-analyzed block specifying a device included in the circuit to be simulated based on input parameters provided from a parameter input means (1), divides the selected to-be-analyzed block into a plurality of to-be-analyzed sub-blocks, establishes an electric connection between the plurality of to-be-analyzed sub-blocks so as to provide a circuit configuration equivalent to the to-be-analyzed block, and finally outputs a modified netlist (D2) defining a new circuit to be simulated in which the to-be-analyzed block is replaced with the plurality of to-be-analyzed sub-blocks. A circuit simulation means (3) performs a circuit simulation on the new circuit to be simulated which is defined by the modified netlist (D2). A device for and method of simulation provides a simulation result which reflects the shape of the device in a short period of calculation time.

Abstract: A method of selecting the optimum mix of resources for achieving an outcome while minimizing risk is presented. In one embodiment, the method is applied to selecting the optimum mix of manufacturing technologies and amount of use of each technology for fabricating a helicopter fuselage structure in order to minimize the recurring cost and keep the risk below a pre-selected value. The method involves selecting a plurality of resources which can be used to achieve the desired outcome. Determining an associated outcome for each resource. Establishing at least one target risk level for the desired outcome. Calculating an associated outcome and risk for a plurality of combinations of the resources at a plurality of percentage applications of each resource. Then determining an optimum mix of resources and percentage of application of each resource which maximizes the outcome while maintaining the risk below the at least one target risk level.

Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.

Abstract: A computer implemented method and system for simulating strategic planning and operations uses an operations control language (OCL) which has the characteristics of: (a) a target expression, (b) a condition expression, (c) an integer hierarchical priority level, (d) at least one penalty expression, and (e) a value expression. The OCL is a high level programming language for describing operating policies for simulation models, such as those used in water resources management. The OCL of the invention is written into a simple text file. The OCL has syntax, keywords and Boolean and arithmetic operators.

Abstract: A method and system for optimizing the execution of a collection of related modules by eliminating redundant modules from the collection. The collection of modules represent a set of related simulation experiments and are organized as generations of related module sequences having execution interdependencies. The method eliminates redundant modules in the collection by redefining execution interdependencies among the modules. Groups of equivalent modules are formed by comparing the modules within each generation to each other to determine which modules are equivalent. Modules having equivalent execution prerequisites and which will produce the same output given the same input are considered equivalent. In each group of equivalent modules, a single “target” module is selected to substitute for the others in the module execution sequences, and execution interdependencies are redefined to effect the substitution.

Abstract: A system having a high efficiency of operation to determine a design rule and thus requiring lesser time needed in determining the design rule, is provided by automating the process of determining the design rule. The system comprises an automatic L/S pattern generation part automatically generating a L/S pattern defined by a line width and space width, an optical simulation part performing an optical simulation based on the L/S pattern and a finish prediction part in which the dimension (finished size) of a pattern formed on a resist is predicted based on the result of the optical simulation. Also included is a L/S matrix database construction part in which a L/S matrix is made based on the finish prediction result, and also constructs the data used in making the L/S matrix, as a database, and a design rule generation part generating a design rule from the L/S matrix.

Abstract: In a method of extracting parameters of a diffusion model from object parameters to be used in a process simulation of a semiconductor manufacturing process, classifying the object parameters into a first through an N-th (N being a natural integer not smaller than 2) groups, the first group being used for classifying thereinto the most fundamental physical and least model-dependent parameters, the N-th group being used for classifying thereinto the least fundamental physical and most model-dependent parameters, and extracting successively the classified parameters in the first through the N-th groups in the order from the first to the N-th group.

Abstract: A procedure and processor are disclosed for avoiding lengthy delays in debug procedures during access by a memory mapped peripheral device. The processor includes in-circuit emulation means comprising one or more scan chains or serially connected registers for access by an external host computer system. The procedure comprises: a) the host computer system carrying out a debug procedure via said scan chains, and selectively interrupting such debug procedure for access to a peripheral memory mapped device; b) the host computer system writing into an area or memory of the processor a program for reading and/or writing data at a specified memory location; and c) the host computer system causing said processor to run said program, and then to return to said debug procedure.

Abstract: A method and apparatus for transferring information between first and second devices, where the first device includes a tape drive having a tape drive head. A tape head interface is removably positionable adjacent the tape drive head to communicate with the tape drive head, and a communications interface communicates signals between the tape head interface and the second device. A tape emulator in communication with the tape head interface emulates a tape in the tape drive.

Abstract: A method for controlling I/O in a multi-processor environment, comprising the steps of: determining if an I/O instruction requiring an interrupt is being executed by one of the processors in the multi-processor environment to transfer data or a command between the processor and an I/O device; performing an interrupt if such an I/O instruction is detected; determining which of the processors in the multi-processor environment is executing an I/O instruction; if only one of the processors is executing an I/O instruction, setting a Last Processor indicator designating that one processor as the processor executing the I/O instruction; and transferring data or a command between the processor designated in the Last Processor indicator and the I/O device in response to the I/O instruction.

Abstract: In a CAD-data management system for managing a plurality of types of CAD data: a plurality of CAD-data processing units are capable of processing a plurality of predetermined types of CAD data, respectively: a processing-request generation unit receives a manipulation input designating CAD data of one of the plurality of types, and generates a processing request corresponding to the manipulation input and being directed to one of the plurality of CAD-data processing units which is capable of processing CAD data of the one of the plurality of types; and a linkage processing unit executes processing defined in a function in conjunction with the one of the plurality of CAD-data processing units, where the function is predefined corresponding to the processing request.

Abstract: A method for applying design for reliability into design for Six Sigma is described. The method includes establishing an appropriate model for reliability as a function of time; determining a reliability transfer function; calculating defects per opportunity per unit of time; entering said defects per opportunity per unit of time into a calculation of value of sigma; selecting one or more noise factors likely to have an impact on reliability; and performing a closed form analytical solution of said impact on reliability using a Monte Carlo analysis. The noise parameters may include one or more assumptions of the hours of usage per year, temperature of use, material quality, part quality, layout of components, extrinsic stresses, supplier quality, interconnection quality, test coverage, shipping damage, installation errors, errors in instructions, customer misuse or other noise factors beyond the control of the designer.

Abstract: The present invention provides a method and apparatus for testing architectural compliance of processors wherein various types of cases requiring some structure can be simulated and a degree of randomness can be added to the case without destroying the structure of the case. The apparatus comprises a computer capable of being configured to execute a testing program. When the computer is executing the testing program, the computer generates instructions and simulates execution of the instructions in a processor. During simulation, the computer detects when simulation of an instruction has caused an event to occur in the processor. The computer identifies the event that has occurred and generates a list of atoms and stores the list in a memory device in communication with the computer. Each of the atoms in the list corresponds to a description of a particular event handler task to be performed by the processor in response to the occurrence of the event.

Abstract: A novel test structure is described which can be used to accurately measure on-wafer impedances. For example, accurate measurements of the parasitic capacitances inside active devices such as Field Effect Transistors or the capacitance of interconnect lines with either the substrate or with each other can be made. The test technique involves frequency sweep S-parameter power measurements made in the range of 50 MHz to about 20 GHz. One or more identical copies of the DUT are connected on the wafer with one or more on-wafer inductances which are usually lumped, to form a two port circuit. The circuit is essentially a filter operating in the frequency range of 50 MHz to 20 GHz. Although filter circuits are normally designed to provide a flat response in the pass and stop bands, with as sharp a skirt as possible, the objective in designing this test circuit is to design a filter response with sharp inflection points that are uniquely dependent on the reactances that comprise the filter circuit.

Abstract: A production process is used to mass-produce chips, each chip being formed in a substrate of a wafer and having an integrated circuit, each integrated circuit having a plurality of primitive device model types. The integrated circuits are produced using a statistical device model for the production process, which is derived from the sets of e-test data.

Abstract: A mixed-mode simulator for simulating a circuit containing an event-driven device with a plurality of pins. The mixed-mode simulator has a circuit simulator for simulating at least an analog portion of the circuit. The circuit simulator has a user-defined device modeling feature. The mixed-mode simulator has an event-driven device simulator and an interface between the circuit simulator and the event-driven device simulator. The interface has a parameter passing portion for receiving values from and returning values to the circuit simulator through the user-defined device modeling feature. The interface has a timing portion for instructing the event-driven simulator to run a simulation of the device based on the values for a given time period. The interface has a response reading portion for reading values of the pins at the end of the time period. Values are returned to the circuit simulator through the parameter passing portion and the user-defined modeling feature.

Abstract: A variational inference engine for probabilistic graphical models is disclosed. In one embodiment, a method includes inputting a specification for a model that has observable variables and unobservable variables. The specification includes a functional form for the conditional distributions of the model, and a structure for a graph of model that has nodes for each of the variables. The method determines a distribution for the unobservable variables that approximates the exact posterior distribution, based on the graph's structure and the functional form for the model's conditional distributions. The engine thus allows a user to design, implement and solve models without mathematical analysis or computer coding.

Abstract: A system and method which reduce a network cost of a domino circuit. The network costs of domino circuits can be reduced by utilizing the methods and systems disclosed. The domino circuit is represented as a mixed integer linear program. The mixed integer linear program is solved to determine an implementation that includes determining a final phase assignment that reduces the network cost.

Abstract: Efficient data modeling utilizing sparse representation of a data set. In one embodiment, a computer-implemented method such that a data set is first input. The data set has a plurality of records. Each record has at least one attribute, where each attribute has a default value. The method stores a sparse representation of each record, such that the value of each attribute of the record is stored only if the value of the attribute varies from the default value. A data model is then generated, utilizing the sparse representation, and the model is output. The generation of the data model in one embodiment is in accordance with the Expectation Maximization (EM) algorithm.