Abstract: It is possible to reduce analysis cost of a management system. The management system includes a CPU and manages one or more storage devices that provide, to a higher-level device, one or more volumes for inputting and outputting data. The CPU is configured to collect performance information of the volume from the storage device at a predetermined first time interval and detect a QoS violation of the performance information of the volume at a second time interval longer than the first time interval.

Abstract: A method for distributed file deletion or truncation, performed by a storage system, is provided. The method includes determining, by an authority owning an inode of a file, which authorities own data portions to be deleted, responsive to a request for the file deletion or truncation. The method includes recording, by the authority owning the inode, the file deletion or truncation in a first memory, and deleting, in background by the authorities that own the data portions to be deleted, the data portions in one of a first memory or a second memory. A system and computer readable media are also provided.

Abstract: An interface of a memory sub-system can receive a write command addressed to a first address and a read command addressed to a second address and can receive data corresponding to the write command. The interface can determine whether the first address matches the second address responsive to determining that the first address matches the second address, can drop the read command and the second address, and can provide the data to a host.

Abstract: A method includes determining respective memory access counts of a plurality of blocks of non-volatile memory cells that are grouped into a plurality of respective groups, comparing the respective memory access counts to respective memory access thresholds, determining a respective memory access count of a block of non-volatile memory cells exceeds a respective memory access threshold, and performing a media scan operation on the block of non-volatile memory cells.

Abstract: A memory system includes a memory device including a plurality of memory dies that store data, and a controller coupled to the plurality of memory dies through a plurality of channels, and suitable for generating and managing map data in which a logical address of a host is corresponding to a physical address of the memory device, wherein, when logical information on two or more consecutive logical addresses requested to be accessed and physical information on two or more consecutive physical addresses corresponding to the two or more consecutive logical addresses are inputted from the host, the controller sequentially performs access operations on the physical addresses corresponding to the received physical information.

Abstract: Disclosed approaches for emulating flash memory include storage circuits having respective address decoders. An input-output circuit has pins compatible with a flash memory device and is configured to input flash commands and output response signals via pins. An emulator circuit is configured to translate each flash command into one or more storage-circuit commands compatible with one storage circuit of the storage circuits, and to generate response signals compatible with the flash memory device. A translator circuit is configured to map a flash memory address in each flash command to an address of the one storage circuit, and to transmit the one or more storage-circuit commands and address to the one storage circuit.

Abstract: A method of operating a controller for controlling a memory device that comprises a plurality of memory cell blocks including outputting block address information based on reliability information for each of the memory cell blocks, providing a patrol read command to the memory device, and controlling the memory device to perform the patrol read operation in response to the patrol read command wherein the block address information comprises an order of the patrol read operation for the memory cell blocks based on the reliability information may be provided.

Abstract: Memory bank redistribution based on power consumption of multiple memory banks of a memory die can provide an overall reduced power consumption of a memory device. The respective power consumption of each bank can be determined and memory operations to the banks can be distributed based on the determined power consumption. The memory die can include an interface coupled to each bank. Control circuitry can remap logical to physical addresses of the banks based on one or more parameters such as a power consumption of each bank, counts of memory operations for each bank, and/or a relative physical distance of each bank.

Abstract: The disclosed technology relates to determining physical zone data within a zoned namespace solid state drive (SSD), associated with logical zone data included in a first received input-output operation based on a mapping data structure within a namespace of the zoned namespace SSD. A second input-output operation specific to the determined physical zone data is generated wherein the second input-output operation and the received input-output operation is of a same type. The generated second input-output operation is completed using the determined physical zone data within the zoned namespace SSD.

Abstract: A memory-control logic, disposed in a memory circuit, is provided. The memory circuit includes a memory-cell array that is divided into a plurality of regions that include a damaged region. The memory-control logic includes a one-time-programmable (OTP) memory array, an array-control circuit, and an address-redirecting circuit. The array-control circuit programs a memory-size type of the memory-cell array, a region-failure flag corresponding to each region, and a redirecting mapping table corresponding to each region in the OTP memory array. The array-control circuit programs the redirecting mapping table corresponding to each region according to the memory-size type to direct the redirecting mapping table corresponding to each damaged region to non-repetitive good regions.

Abstract: A storage system in one embodiment comprises a front-end device and a first storage node corresponding to the front-end device. The first storage node comprises a processor that is separate from the front-end device. The front-end device is configured to obtain a write operation that comprises at least a first block of data and to calculate a hash digest based at least in part on the first block of data. The front-end device is configured to provide the hash digest to the processor. The processor is configured to identify a first data page that comprises a second block of data that is a target for replacement by the first block of data and to identify a second storage node based at least in part on the first data page. The processor is configured to transmit the hash digest to the second storage node.

Abstract: A system comprising a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations including initializing a block family associated with the memory device and measuring an opening temperature of the memory device at initialization of the block family. Responsive to programming a page residing on the memory device, the operations further include associating the page with the block family. The operations further include determining a temperature metric value by integrating, over time, an absolute temperature difference between the opening temperature and an immediate temperature of the memory device. The operations further include closing the block family in response to the temperature metric value being greater than or equal to a specified threshold temperature value.

Abstract: A system and method for efficiently reducing the latency of load operations. In various embodiments, logic of a processor accesses a prediction table after fetching instructions. For a prediction table hit, the logic executes a load instruction with a retrieved predicted address from the prediction table. For a prediction table miss, when the logic determines the address of the load instruction and hits in a learning table, the logic updates a level of confidence indication to indicate a higher level of confidence when a stored address matches the determined address. When the logic determines the level of confidence indication stored in a given table entry of the learning table meets a threshold, the logic allocates, in the prediction table, information stored in the given entry. Therefore, the predicted address is available during the next lookup of the prediction table.

Abstract: Techniques for storage management involve determining, in response to a detection that a disk changes from an unavailable state to an available state, at least one candidate storage unit associated with the disk; acquiring historical access information about the at least one candidate storage unit, the historical information comprising information related to a write request directed to the at least one candidate storage unit when the disk is in the unavailable state; determining a target storage unit from the at least one candidate storage unit based on the historical access information; and rebuilding the target storage unit. Such techniques may, in a low-cost manner, improve rebuilding efficiency and reliability of a storage system.

Abstract: A storage system analyzes a logical block address range of data in a resolution of a defragmentation unit. The storage system determines whether a given defragmentation unit is fragmented above a threshold and performs a defragmentation operation accordingly. Additionally or alternatively, the storage system can receive a suggested logical block address read order from a host to improve performance.

Abstract: Summarizing the invention, a computer-implemented method is provided. The computer-implemented method comprises: allocating, by an operating system kernel, a physical memory block for a privileged function; storing, by the operating system kernel, the privileged function in the physical memory block; creating, by the operating system kernel, an entry for the physical memory block in a mapping table, wherein the entry associates the physical memory block to a virtual memory block in an address space of a program; setting, by the operating system kernel, a security bit for the entry in the mapping table; executing, by a processor, the program in unprivileged mode; and if the program requests the privileged function: checking, by the processor, whether the security bit is set; if the security bit is set, switching, by the processor, execution to kernel mode for performing the privileged function.

Abstract: Non-volatile Random Access Memory (NVR) on a storage system may be dynamically converted between use as temporary memory in a memory context and use as persistent memory in a storage context. NVR (e.g., embodied as DIMM) may be utilized in a hybrid capacity, where some of the NVR is used as memory and some of the NVR is used as storage, and where NVR memory is converted to memory as needed, dynamically as I/O is being processed using the NVR. A host system may be directly connected to an internal switching fabric of the data storage system without an intervening component of the storage system (e.g., a director) controlling access of the host system to the internal fabric or to the memory. The host system may provision and use the NVR as storage by directly communicating with the NVR over the internal fabric, for example, using RDMA.

Abstract: A storage device includes a first memory device including a plurality of first memory cells, a second memory device including a plurality of second memory cells having the same type as the plurality of first memory cells, and a controller that communicates with the first memory device through a first memory interface and communicates with the second memory device through a second memory interface having an operating speed higher than an operating speed of the first memory interface.

Abstract: A computer-implemented method that includes managing a buffer pool of pages into a ring sub-chain comprising pages linked in a ring, and a linear sub-chain comprising pages linked in a line from a header, and moving a page between the linear sub-chain and the ring sub-chain based on a moving schema evaluating a chain management characteristic.

Abstract: In a method of generating a signal for test in a memory device configured to output a multi-level signal, an operation mode is set to a first test mode. During the first test mode, first data bits included in a plurality of test data are arranged based on a first scheme. Each of the plurality of test data includes two or more data bits. During the first test mode, a first test result signal having two voltage levels is generated based on the first data bits according to the first scheme. The operation mode is set to a second test mode during which second data bits included in the plurality of test data are arranged based on a second scheme. During the second test mode, a second test result signal having the two voltage levels is generated based on the second data bits according to the second scheme.