Abstract: A system, method, and computer program product is described for providing dynamic enabling and/or disabling of protection information (PI) in array systems during operation. A storage system receives a request to transition a volume from PI disabled to PI enabled during regular operation. The storage system synchronizes and purges the cache associated with the target volume. The storage system initiates an immediate availability format (IAF-PI) process to initialize PI for the associated data blocks of the volume's storage devices. The storage system continues receiving I/O requests as the IAF-PI process sweeps through the storage devices. The storage system inserts and checks PI for the write data as it is written to the storage devices. The storage system inserts PI for requested data above the IAF-PI boundary and checks PI for requested data below the IAF-PI boundary. The transition remains an online process that avoids downtime.

Abstract: Persistent storage for a master copy is provided using operation numbers. A master copy can include a persistent key-value store such as a B-tree with references to corresponding data. When provisioning a slave copy, the master copy sends a point-in-time copy of the B-tree to the slave copy, which stores a copy of the B-tree, allocates the necessary space, and updates the references of the B-tree to point to a local storage before the data is transferred. When writing the data to persistent storage, a snapshot created on the master copy is an operation that is replicated to the slave copy. The snapshot is generated using a volume view that includes changes to chunks of data of the master copy since a previous snapshot, as determined using the operation number for the previous snapshot. Data (and metadata) for the snapshot is written to persistent storage while new EO operations are processed.

Abstract: A storage system includes a plurality of storage devices, including a first storage device and an information processor apparatus for managing the storage system. The first storage device is configured to select a second storage device coupled over a network with the information processor apparatus from among the plurality of storage devices, and assign a representative address such as an Internet Protocol (IP) address to be used for communication with the information processor apparatus to the selected second storage device. The second storage device is configured to receive a request addressed to the representative address from the information processor apparatus, and transfer the request to a third storage device among the plurality of storage devices to process the request. An assigned representative address may be canceled when a storage device fails and an internal IP address may be assigned. Storage devices may be selected based on load and the need for cable or hardwired connections may be reduced.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

Abstract: A system is provided for transforming an in-use RAID array from a first array configuration having a first parameter to a second array configuration having a second parameter while preserving a logical data structure of the RAID array. The system includes an extent reservation component, and a data migration component for reading unmigrated data from an area of an array arranged according to the first array configuration and writing the data to an area of the array arranged according to the second array configuration using reserved extents to store migrated data. The system also includes a first I/O component for performing I/O according to the first array configuration on unmigrated data prior to its reading by the data migration component, and a second I/O component for performing I/O according to the second array configuration on the migrated data after writing the migrated data.

Abstract: An administrator provisions a virtual disk in a remote storage platform and defines policies for that virtual disk. A virtual machine writes to and reads from the storage platform using any storage protocol. Virtual disk data within a failed storage pool is migrated to different storage pools while still respecting the policies of each virtual disk. Snapshot and revert commands are given for a virtual disk at a particular point in time and overhead is minimal. A virtual disk is cloned utilizing snapshot information and no data need be copied. Any number of Zookeeper clusters are executing in a coordinated fashion within the storage platform, thus increasing overall throughput. A timestamp is generated that guarantees a monotonically increasing counter, even upon a crash of a virtual machine. Any virtual disk has a “hybrid cloud aware” policy in which one replica of the virtual disk is stored in a public cloud.

Abstract: The memory area managing unit 22 (a) sets a protect flag to each virtual area allocated in a virtual memory space, the protect flag indicating whether a use of the virtual area has been finished or not, and (b) when a part or all of a first virtual area would overlap another second virtual area due to expansion or movement of the first virtual area, allows the expansion or the movement of the first virtual area accompanying with overlapping the second virtual area, if the protect flag of the second virtual area indicates that a use of the second virtual area has been finished. If the expansion or the movement is allowed, the memory pool managing unit 23 adds a physical area in a physical memory space corresponding to an overlapping part of the first and second virtual areas into a memory pool to map to another virtual area.

Abstract: An electronic device includes a semiconductor device, wherein the semiconductor device includes: a word line driving unit for driving a plurality of word lines; a first cell array arranged at one side of the word line driving unit; a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit, arranged between the first cell array and the second cell array, for generating a bias voltage based on currents flowing through the first reference resistance element included in the first cell array and the second reference resistance element included in the second cell array; a first read control unit; and a second read control unit.

Abstract: A solid state memory unit and method for protecting a solid state memory having a microprocessor are disclosed. The method may include receiving user-input requests for access to blocks of the solid state memory, the blocks of the solid state memory storing ordered virtual files. The user-input requests may have a respective sequence of virtual file position values. The method may include comparing the sequence of virtual file position values with a predetermined sequence of virtual file position values to verify the user-input requests, and when the sequence of virtual file position values equals the predetermined sequence of virtual file position values, responding to, via the microprocessor, requests for access to the blocks of the solid state memory to decrypt and transfer requested files stored. The predetermined sequence may correspond to a predetermined sequence of requests for access to files that can be selected by the user.

Abstract: A disk drive includes a controller and at least one disk, which may include a first I-region, a second I-region, and an E-region. The first and second I-region may have a first final logical block address (LBA) and a second final LBA, respectively. The controller may be configured to cause information to be written to the first I-region and the second I-region using a first type and a second type of magnetic recording, respectively. The controller also may be configured to set at least one of the first final LBA or the second final LBA to a final LBA value higher than the at least one of the first final LBA or the second final LBA, respectively, after writing user data to at least a portion of the first I-region or the second I-region and without removing the user data.

Abstract: A data storage device with a FLASH memory accessed via multiple channels and a FLASH memory control method are disclosed. The control method includes dividing a plurality of blocks of a FLASH memory into groups to be accessed by a plurality of channels separately, each block comprising a plurality of pages; allocating a random access memory to provide a first set of cache spaces for the different ones of the plurality of channels; separating write data issued from a host to correspond to the plurality of channels; and after data arrangement in the first set of cache spaces for every channel is completed, writing data arranged in the first set of cache spaces for every channel to the FLASH memory via the plurality of channels.

Abstract: A non-transitory computer-readable recording medium has stored therein a program for causing a computer to execute a process. The process includes identifying a data block from among a plurality of data blocks in a first storage for relocation to a second storage, determining an access mode of the identified data block, the access mode including sequential access or random access, and relocating the identified data block to the second storage based on the determined access mode.

Abstract: A processor may include a memory controller to interface with a system memory having a near memory and a far memory. The processor may include logic circuitry to cause memory controller to determine whether a write request is generated remotely or locally, and when the write request is generated remotely to instruct the memory controller to perform a read of near memory before performing a write, when the write request is generated locally and a cache line targeted by the write request is in the inclusive state to instruct the memory controller to perform the write without performing a read of near memory, and when the write request is generated locally and the cache line targeted by the write request is in the non-inclusive state to instruct the memory controller to read near memory before performing the write.

Abstract: A storage control device of an outboard motor writing operation history information of the outboard motor to a nonvolatile memory by using an electric power generated by driving of an internal combustion engine, the storage control device includes a stop instruction detecting unit detecting a stop instruction of the driving of the internal combustion engine by a boat operator, a writing unit writing the operation history information to the nonvolatile memory in accordance with the stop instruction detected by the stop instruction detecting unit, a write judgment unit judging whether or not the operation history information is written to the nonvolatile memory by the writing unit, and a stop processing unit stopping the driving of the internal combustion engine after it is judged that the operation history information is written to the nonvolatile memory by the write judgment unit.

Abstract: In one embodiment, a method for controlling an instruction cache including a least-recently-used bits array, a tag array, and a data array, includes looking up, in the least-recently-used bits array, least-recently-used bits for each of a plurality of cacheline sets in the instruction cache, determining a most-recently-used way in a designated cacheline set of the plurality of cacheline sets based on the least-recently-used bits for the designated cacheline, looking up, in the tag array, tags for one or more ways in the designated cacheline set, looking up, in the data array, data stored in the most-recently-used way in the designated cacheline set, and if there is a cache hit in the most-recently-used way, retrieving the data stored in the most-recently-used way from the data array.

Abstract: A memory device includes a substrate, a plurality of nonvolatile memory chips disposed on the substrate, and a memory controller disposed on the substrate. The memory chips may be disposed on the same side or the opposite side of the substrate as the memory controller. The memory controller controls each of the nonvolatile memory chips based on a firmware, where the firmware is written in a nonvolatile memory chip positioned at a location farthest from the memory controller. A write system may perform writing using a binary or single level cell (SLC) recording system in memory chips located closest to the memory controller and a multi-value or multi-level cell (MLC) recording system in memory chips located farthest from the memory controller. A weighting factor may be assigned for each of the nonvolatile memory chips based on the distance from the memory controller.

Abstract: A storage system is dynamically reconfigured. The storage system includes storage pools that each include one or more storage disks. Storage pools to be expanded are determined as target storage pools. For the target storage pools, source storage disks to be moved into the target storage pools are determined from other storage pools than the target storage pools in the storage system. The source storage disks are migrated to the respective target storage pools.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a resource managing unit that reclaims resources associated with the non-volatile memory and increases the resources, when the usage of the resources associated with the non-volatile memory reaches the predetermined amount, a transmission rate setting unit that calculates a setting value of the transmission rate to receive the write data from a host device, and a transmission control unit that receives the write data from the host device and transmits the received write data to the non-volatile memory. The transmission rate setting unit calculates a small setting value when the usage of the resources associated with the non-volatile memory increases. The transmission control unit executes the reception of the write data from the host device at the transmission rate of the setting value, while the resource managing unit reclaims the resources.

Abstract: A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation.

Abstract: A method includes determining a size of a recommended spare memory space of each of one or more storage nodes based on a state of the storage nodes, and adjusting a spare memory space of each of the storage nodes based on the size of the recommended spare memory space.