Patents Examined by Sanjiv Shah
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Patent number: 11150810Abstract: Embodiments of the present disclosure relate to a method for I/O data transmission in a Hyper-Converged Storage System (HCSS). The HCSS comprises at least one storage node having at least one device constructed with virtualization technology and a storage I/O processing module for accessing persistent storage resource of the HCSS. According to the method, an I/O request of a first type is received from the device by a System Disk front-end driver (SFD), wherein the I/O request of the first type is an I/O request to a system disk of the device. The I/O request of the first type and its corresponding response of a first type are transferred by the SFD between the device and the storage I/O processing module via a first shared memory, wherein the first shared memory is created by allocating a first memory region of the HCSS as the first shared memory.Type: GrantFiled: January 26, 2018Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Long Wen Lan, Jia Xiang Li, Yang Li, Zhuo Liu, Wen Wu Na
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Patent number: 11144229Abstract: An apparatus in one embodiment comprises at least one processing device comprising a processor coupled to a memory. The processing device is configured to identify a storage volume to be migrated from a source storage system to a target storage system, and for each of a plurality of logical addresses of the storage volume, to send a command requesting a content-based signature for the logical address to at least one of the source storage system and a host device and to receive the content-based signature in response to the command. Responsive to a first one of the received content-based signatures having a corresponding data page already stored in the target storage system, the processing device updates an associated reference count in place of requesting the corresponding data page. Responsive to a second one of the received content-based signatures not having a corresponding data page already stored in the target storage system, the processing device requests the corresponding data page.Type: GrantFiled: November 1, 2018Date of Patent: October 12, 2021Assignee: EMC IP Holding Company LLCInventors: Anton Kucherov, David Meiri
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Patent number: 11137931Abstract: Backup metadata deletion based on backup data deletion is described. A system receives a request to delete a backup data set associated with a host, a path, and a backup time. The system identifies a backup metadata object associated with the host and the path. The system determines whether the requested backup time is the earliest backup time associated with any backup data set associated with the host. The system determines whether the identified backup metadata object is a backup metadata deletion object associated with the backup time if the backup time is the earliest backup time. The system deletes the identified backup metadata object if the identified backup metadata object is a backup metadata deletion object associated with the backup time.Type: GrantFiled: July 1, 2016Date of Patent: October 5, 2021Assignee: EMC IP Holding Company LLCInventors: Ynn-Pyng Tsaur, Venu Varma
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Patent number: 11126368Abstract: A method for finding a last good page in a memory system includes determining a first number of write operations in a first queue at a first page in a memory block of the memory system. The method also includes determining whether the first number of write operations in the first queue is above a threshold. The method also includes based on a determination that the first number of write operations in the first queue is above the threshold, determining whether a second page in the memory block is empty. The method also includes identifying, based on a determination that the second page is empty, the last good page in the memory block using a binary search between the first page and the second page.Type: GrantFiled: April 30, 2019Date of Patent: September 21, 2021Assignee: Western Digital Technologies, Inc.Inventors: Tomer Eliash, Evgeny Mekhanik, David Rozman, Yair Chasdai
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Patent number: 11126544Abstract: A non-volatile memory (NVM) apparatus and a garbage collection method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller is coupled to the NVM. The controller accesses the NVM according to a logical address of a write command of a host. The controller performs the garbage collection method to release space occupied by invalid data. The garbage collection method includes: grouping a plurality of blocks of the NVM into a plurality of tiers according to hotness of data, moving valid data in one closed source block of a hotter tier among the tiers to one open target block of a cooler tier among the tiers, and erasing the closed source block of the hotter tier to release space.Type: GrantFiled: December 14, 2016Date of Patent: September 21, 2021Assignee: VIA Technologies, Inc.Inventors: Ying Yu Tai, Jiangli Zhu
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Patent number: 11126451Abstract: A technique includes changing a configuration setting of a virtual volume of data stored in a storage system. The technique includes converting data of the virtual volume in place to reflect the changing of the configuration setting.Type: GrantFiled: October 24, 2017Date of Patent: September 21, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Siamak Nazari, Srinivasa D. Murthy
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Patent number: 11119943Abstract: A memory management unit comprises an interface for receiving an address translation request from a device, the address translation request specifying a virtual request to be translated. Translation circuitry translates the virtual address into an intermediate address different from a physical address directly specifying a memory location. The interface provides an address translation response specifying the intermediate address to the device in response to the address translation request. This improves security by avoiding exposure of physical addresses to the device.Type: GrantFiled: February 9, 2016Date of Patent: September 14, 2021Assignee: Arm LimitedInventor: Matthew Lucien Evans
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Patent number: 11086522Abstract: Automated port selection for data migration includes an algorithm that selects a set of SAN ports with the following properties: the selected ports have the least port utilization among all possible port selections; the number of independent data paths between the selected ports is no smaller than a user configurable minimum number; and the difference between the aggregate bandwidth of the ports on both arrays is minimized.Type: GrantFiled: September 23, 2016Date of Patent: August 10, 2021Assignee: EMC IP HOLDING COMPANY LLCInventors: Xuedong Jiang, John Copley, Michael Specht
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Patent number: 11023318Abstract: A system and method is provided for fast random access erasure encoded storage. An exemplary method includes writing data to an append-only data log that includes data log extents that are each associated with data that is mapped to corresponding offset range of a virtual file of a client and storing the append-only data log as a sequence of data chunks each allocated on one or more one storage disks. Moreover, the method determines an amount of useful data in one or more data chunks and, when the amount of useful data in the data chunk is less than a predetermined threshold, appending the useful data from the data chunk to an end of the append-only data log. Finally, the data log is cleaned by releasing the one or more data chunk from the append-only data log after the useful data is appended to the append-only data log.Type: GrantFiled: June 21, 2018Date of Patent: June 1, 2021Assignee: Virtuozzo International GmbHInventors: Oleg Volkov, Andrey Zaitsev, Alexey Kuznetzov, Pavel Emelyanov, Alexey Kobets, Kirill Korotaev
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Patent number: 11016676Abstract: Systems, methods, and computer program products for distributed data storage. A spot defragmentation method commences upon receiving an incoming storage I/O command to access a subject logical object that is composed of subject logical data blocks. The method continues by retrieving a block map that characterizes spatial relationships between the subject logical data blocks and instances of respective subject physical data blocks that store the subject logical object on a storage device. During processing of the incoming storage I/O command, the method determines occurrences of, and locations of one or more fragmented physical data blocks. A defragmentation operation is initiated to coalesce the fragmented physical data blocks to another location. The defragmentation operation is initiated before completing the storage I/O command.Type: GrantFiled: February 9, 2016Date of Patent: May 25, 2021Assignee: Nutanix, Inc.Inventors: Manosiz Bhattacharyya, Bharat Kumar Beedu, Parthasarathy Ramachandran
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Patent number: 10996898Abstract: A storage system in one embodiment comprises a plurality of storage devices and an associated storage controller. The storage controller is configured to identify a dataset to be scanned to generate a capacity release estimate for prospective deletion of that dataset, to designate a content-based signature prefix to be utilized in the scan, and to scan logical address mapping information for the dataset to identify one or more pages of the dataset that have the designated content-based signature prefix. The scanning further comprises, for each such identified page, determining a reference count of the page, and responsive to the reference count of the page having a particular value, determining a compressibility measure for the page. The storage controller generates the capacity release estimate for prospective deletion of the dataset based at least in part on the one or more page compressibility measures determined as part of the scan.Type: GrantFiled: May 29, 2018Date of Patent: May 4, 2021Assignee: EMC IP Holding Company LLCInventors: David Meiri, Anton Kucherov
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Patent number: 10866757Abstract: A production host for hosting a multi-instanced application includes a persistent storage and a resource manager. The persistent storage stores a resource registration associated with a plurality of instances of the multi-instanced application and a resource backup registration associated with backups, of the multi-instance application, that are stored in backup storage.Type: GrantFiled: September 26, 2018Date of Patent: December 15, 2020Assignee: EMC IP Holding Company LLCInventors: Jigar Premajibhai Bhanushali, Sunil Yadav, Aneesh Kumar Gurindapalli, Sunder Ramesh Andra, Amarendra Behera, Shelesh Chopra
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Patent number: 10740005Abstract: Described are techniques for processing requests at a data storage system. A request is received from a client to perform an operation with respect to a first data portion stored on physical storage devices of the data storage system. The first data portion is exposed through a set of at least two data nodes each accessing a same copy of the first data portion stored on the physical storage devices. The request is received at a first of the data nodes of the set. The request is processed with respect to the first data portion using the same copy accessible to each of data nodes of the set. The physical storage devices may be configured in a RAID group and the data nodes, optionally along with a name node providing metadata, may be embedded in the data storage system and execute in a virtualized environment.Type: GrantFiled: September 29, 2015Date of Patent: August 11, 2020Assignee: EMC IP Holding Company LLCInventors: Stephen Richard Ives, Hongliang Tang, Kevin Rodgers, Sethu N. Madhavan
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Patent number: 10713190Abstract: Disclosed approaches for managing a translation look-aside buffer (TLB) have a bus master circuit that issues a read request that specifies a first virtual address of a first page. In response to a sequential access being identified and before data of the first page is returned, the bus master circuit issues a dummy read request that specifies a second virtual address of a second page. A TLB has mappings of virtual addresses to physical addresses, and a translation logic circuit translates virtual addresses to physical addresses. The translation logic circuit signals a miss in response to absence of a virtual address in the TLB. A control circuit in the MMU determines from a page table a mapping of a virtual address to a physical address in response to the signaled miss. The translation logic circuit updates the TLB circuit with the mapping.Type: GrantFiled: October 11, 2017Date of Patent: July 14, 2020Assignee: Xilinx, Inc.Inventor: Ygal Arbel
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Patent number: 10262721Abstract: The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel controller coupled to the memory device. The channel controller is configured to cause a bulk invalidate command to be sent to a cache memory system responsive to receipt of a bit vector operation request.Type: GrantFiled: March 10, 2016Date of Patent: April 16, 2019Assignee: Micron Technology, Inc.Inventor: Richard C. Murphy
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Patent number: 9946719Abstract: An apparatus includes a processor component of a first node device caused to receive data block encryption data and an indication of size of an encrypted data block distributed to the first node device for decryption, and in response to the data set being of encrypted data: receive an indication of the quantity of sub-blocks within the encrypted data block, and a hashed identifier for each data sub-block; use the data block encryption data to decrypt the encrypted data block to regenerate data set portions from the data sub-blocks; analyze the hashed identifier of each data sub-block to determine whether all data set portions are distributed to the first node device for processing; and in response to a determination that at least one data set portion is to be distributed to a second node device for processing, transmit the at least one data set portion to the second node device.Type: GrantFiled: September 1, 2017Date of Patent: April 17, 2018Assignee: SAS Institute Inc.Inventors: Brian Payton Bowman, Mark Kuebler Gass, III
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Patent number: 9946718Abstract: An apparatus may include a processor component caused to: generate map entries in map data descriptive of encrypted data blocks within a data file; use first map block encryption data to encrypt a first map extension of the map data; transmit the encrypted first map extension for storage within the data file; store the first map block encryption data within the second map extension; use second map block encryption data to encrypt a second map extension of the map data after storage of the first map block encryption data therein; transmit encrypted second map extension for storage within the data file; store the second map block encryption data within the map base; use third map block encryption data to encrypt a map base of the map data after storage of the second map block encryption data therein; and transmit the encrypted map base for storage within the data file.Type: GrantFiled: September 1, 2017Date of Patent: April 17, 2018Assignee: SAS Institute Inc.Inventors: Brian Payton Bowman, Mark Kuebler Gass, III
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Patent number: 9898361Abstract: Methods and apparatus are provided for multi-tier detection and decoding in flash memory devices. Data from a flash memory device is processed by obtaining one or more read values for at least one bit in a given page of the flash memory device; converting the one or more read values for the at least one bit to a reliability value; performing an initial decoding of the at least one bit in a given page using the reliability value; and performing an additional decoding of the at least one bit in the given page if the initial decoding is not successful, wherein the additional decoding uses one or more of additional information for the given page and at least one value for at least one bit from at least one additional page.Type: GrantFiled: December 31, 2012Date of Patent: February 20, 2018Assignee: Seagate Technology LLCInventors: Erich F. Haratsch, Abdel Hakim S. Alhussien
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Patent number: 9880543Abstract: A method for transmitting and receiving data between a micro processing unit (MPU) and a memory operating with different operating voltages in a programmable logic controller (PLC) is provided. In one embodiment, the method includes outputting, by the MPU, a chip select (CS) signal and an address signal to read requested data from the memory, outputting, by an OR gate, an activation signal for activating a data input buffer, the OR gate receiving the CS signal and the address signal, and outputting, by an access signal output buffer, a memory access signal for operation of the memory, the access signal output buffer receiving the CS signal and the address signal. The method further includes outputting the requested data to the data input buffer, and outputting, by the data input buffer, the requested data to the MPU when the requested data is received by the data input buffer from the memory.Type: GrantFiled: September 25, 2015Date of Patent: January 30, 2018Assignee: LSIS CO., LTD.Inventor: Jo Dong Park
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Patent number: 9870400Abstract: Analyzing a managed runtime cache is provided. A heap associated with a managed runtime environment, where the heap includes an N-generation cache or a plurality of objects associated with a program operating within a managed runtime environment is identified. A snapshot of the heap is produced, wherein the snapshot identifies a memory location for each object of the plurality of objects at which the object is stored. A generation of each of the plurality of objects based, at least in part, on the memory location of the object is determined. One or more suggestions based, at least in part, on the memory location of the plurality of objects is provided.Type: GrantFiled: August 4, 2015Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Richard N. Chamberlain, Howard J. Hellyer, Matthew F. Peters, Adam J. Pilkington