Patents Examined by Sanjiv Shah
  • System and method for providing implicit unmaps in thinly provisioned virtual tape library systems
    Patent number: 9170740
    Abstract: The present invention is a system and method which allows for a VTL system that supports thin provisioning to implicitly unmap unused storage. Such unmap operations may occur even though the VTL system does not receive any explicit unmap requests from its initiators. For example, if a system administrator knows that once a virtual tape drive of the VTL system has been partially overwritten, all previously written data sets on that virtual tape drive will never again be accessed, the system administrator may configure the VTL system so that it unmaps the entire remainder of the virtual tape drive on the first data overwrite.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: October 27, 2015
    Assignee: NetApp, Inc.
    Inventors: Ross Zwisler, Brian McKean, Kevin Kidney
  • Solid state drive interface controller and method selectively activating and deactivating interfaces and allocating storage capacity to the interfaces
    Patent number: 9164703
    Abstract: A solid state drive (SSD) interface controller includes a host interface, first and second command interfaces, and an interface information storage unit. The interface information storage unit is configured to store information for determining activation or deactivation of each of the first and second command interfaces, and a capacity allocated to each of the first and second command interfaces. The interface information storage unit may comprise first and second registers storing interface information, which may be changed in response to an extension ROM BIOS executed during a booting operation. The command interfaces may be configured to communicate using interface protocols such as SATA, SATA express, or nonvolatile express. An interface power management unit may cut power to an interface when deactivated based on the stored interface information.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Jun Shim, Je-Hyuck Song, Kwang Gu Lee
  • Optimization of native buffer accesses in Java applications on hybrid systems
    Patent number: 9158497
    Abstract: Managing buffers in a hybrid system, in one aspect, may comprise selecting a first buffer management method from a plurality of buffer management methods; capturing statistics associated with access to the buffer in the hybrid system running under the initial buffer management method; analyzing the captured statistics; identifying a second buffer management method based on the analyzed captured statistics; determining whether the second buffer management method is more optimal than the first buffer management method; in response to determining that the second buffer management method is more optimal than the first buffer management method, invoking the second buffer management method; and repeating the capturing, the analyzing, the identifying and the determining.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael H. Dawson, Yuqing Gao, Megumi Ito, Graeme Johnson, Seetharami R. Seelam
  • System for dynamically distributing an available memory resource to redundant and non-redundant storage areas using RAM routing logic
    Patent number: 9152511
    Abstract: A system for distributing an available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage. The system may further comprise bus access ports which support at least one of concurrent access by a bus access port to access redundantly stored data or non-redundantly stored data, or concurrent access by at least two bus access ports to respective RAM elements to access redundantly stored data or to a respective one of the RAM elements to access non-redundantly stored data. Comparison logic and error detection or correction logic may be provided to detect or correct errors in information read from the RAM elements.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: October 6, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Rohleder, Gary Hay, Stephan Mueller, Manfred Thanner
  • System and method for performing data retention in solid-state memory utilizing copy commands and usage data
    Patent number: 9135166
    Abstract: Systems and methods for retaining data in non-volatile solid-state memory are disclosed in which refresh copy operations are performed on data stored in non-volatile solid-state memory. A controller can comprise a data retention module configured to issue copy commands within different periods of time and to maintain usage data on a storage subsystem. A refresh copy operation helps ensure that data written to memory retain integrity by causing data to be programmed again onto the memory. Execution of refresh copy commands may be prioritized over other commands based on a remaining length of time. One or more data structures may be used to determine memory blocks that require refresh copy operations. In one embodiment, a validity bit array is used to track blocks that contain valid data. In another embodiment, a least recently used list is used to track blocks that have been least recently written.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 15, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mei-Man L. Syu, Matthew Call, Ho-Fan Kang, Lan D. Phan
  • Semiconductor storage apparatus and method including executing refresh in a flash memory based on a reliability period using degree of deterioration and read frequency
    Patent number: 9129699
    Abstract: A semiconductor storage apparatus comprises a memory controller and flash memories which include a plurality of blocks as storage areas. The memory controller is configured to manage a degree of deterioration and read frequency for each of the plurality of blocks. A reliability maintained period is calculated for each storage area based on the degree of deterioration and read frequency for each storage area of a flash memory, and refresh is executed on each storage area in a planned manner based on the calculated reliability maintained period by newly storing the data stored in a block in another block based on an obtained reliability maintained period. The memory controller may also be configured to execute verification on each block and, if the number of failure bits is larger than a predetermined threshold, execute refresh to store data which is stored in a verification target block in another block.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: September 8, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Akifumi Suzuki, Takashi Tsunehiro
  • Solid state memory and method for protecting digital contents by interrupting copying or accessing and proceeding only upon user verification or authentication
    Patent number: 9129139
    Abstract: A solid state memory including a processor and a method for protecting the digital contents of the solid state memory. The microprocessor inserts at least an interruption during a copying or a reading of the digital contents and proceeds with the copying or reading only subsequent to a verification of a PIN or other user action. In particular, the verification provides control to ensure that the PIN is inserted manually. Access may be prevented if a time elapsed between the interruption and inputting of a PIN is shorter than a threshold time representing a speed of manual input, or if the PIN does not correspond to a sequence of requests for access to selectable files, which may be virtual files. The interruption may comprise substituting altered or cryptographic data if verification fails, or reproduction of an audio or visual message to be understood by the user.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: September 8, 2015
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Francesco Varone, Amedeo Veneroso
  • Transaction splitting apparatus and method
    Patent number: 9104526
    Abstract: A transaction splitting apparatus and method are provided in which neighboring sub-transactions accessing a predetermined bank in each memory may access different banks. The transaction splitting apparatus includes a first processing unit to split a transaction into at least one sub-transaction, the transaction accessing a first bank among a plurality of banks comprised in a memory, and a second processing unit to translate an address of the at least one sub-transaction, to interleave the at least one sub-transaction using the plurality of banks.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: August 11, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Sun Jeon, Ho Jin Lee, Joon Hyuk Cha, Shi Hwa Lee, Young Su Moon, Hyun Sang Park
  • Determining an identification of a disc based on a format of the disc
    Patent number: 9099100
    Abstract: A system, method, and computer-readable storage media for disc identification are disclosed. A first disc format may be identified by matching a sequence of symbols on a disc to format data. Content stored on the disc in a first location that is used to generate IDs for the first disc format may be referenced, and the content processed to generate an ID for the disc. The first location can be identified by referencing ID processing data that also identifies other locations used to generate IDs for different disc formats. Portions of the content that are accessed can include directory names, folder names, or file names.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: August 4, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Aayaz Bhorania, Kyunga Lee
  • Multiple programming of flash memory without erase
    Patent number: 9070453
    Abstract: To store, successively, in a plurality of memory cells, first and second pluralities of input bits that are equal in number, a first transformation transforms the first input bits into a first plurality of transformed bits. A first portion of the cells is programmed to store the first transformed bits according to a mapping of bit sequences to cell levels, but, if the first transformation has a variable output length, only if there are few enough first transformed bits to fit in the first cell portion. Then, without erasing a second cell portion that includes the first portion, if respective levels of the cells of the second portion, that represent a second plurality of transformed bits obtained by a second transformation of the second input bits, according to the mapping, are accessible from the current cell levels, the second portion is so programmed to store the second transformed bits.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: June 30, 2015
    Assignee: Ramot at Tel Aviv University Ltd.
    Inventors: Eran Sharon, Idan Alrod, Simon Litsyn, Ishai Ilani
  • Distributed storage medium management for heterogeneous storage media in high availability clusters
    Patent number: 9063939
    Abstract: A high availability cluster and method of storage medium management in such high availability cluster. A number k of nodes belonging to the cluster, where k?2 and includes a master node, are provisioned with high-access-rate and low-access-rate storage media. A file is written to the high-access-rate medium of a serving node selected from among k?1 nodes excluding the master node. The file is also written to low-access-rate medium of each of k?2 nodes excluding the master node and the serving node. A distributed storage medium management protocol supervises file migration from the low-access-rate medium of a back-up node to the high-access-rate medium of the back-up node upon disruption of file availability on the serving node. File rebalancing relies on parameters including popularity, write- and read-requests, capacity, processing load or cost.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: June 23, 2015
    Assignee: ZETTASET, INC.
    Inventor: Michael W. Dalton
  • Memory system provided with NAND flash memory and method including simultaneously writing data to first and second memory arrays
    Patent number: 9063903
    Abstract: A memory system includes first and second districts, and a control section. Each of the first and second districts includes a memory cell array. The control section receives a single write command to simultaneously write first data to the first and second districts. A memory controller may subsequently issue a read command to read the first data from one of the memory cell arrays to determine whether the read first data is normal or is correctable based on a result of error correction in an error correction circuit. When the read first data is normal or is correctable, the first data written to the other of the memory cell arrays may be deleted or nullified.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: June 23, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi Sukegawa
  • Method and apparatus having a snoop filter decoupled from an associated cache and a buffer for replacement line addresses
    Patent number: 9058272
    Abstract: An apparatus including a snoop filter decoupled from a cache and an associated method for snoop filtering are disclosed. The snoop filter is decoupled from the cache such that the cache changes states of lines in the cache from a first state that is a clean state, such as an exclusive (E) state, to a second state that is not a clean state, such as a modified (M) state, without the snoop filter's knowledge. The snoop filter buffers addresses of replaced lines that are unknown to be clean until a write-back associated with the replacement lines occurs, or until actual states of the replaced lines are determined by the snoop filter generating a snoop. A multi-level cache system in which a reallocation or replacement policy is biased to favor replacing certain lines such as inclusive lines, non-temporal lines or prefetched lines that have not been accessed, is also disclosed.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: June 16, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Frank O'Bleness, Sujat Jamil, David Miner, Joseph Delgross, Tom Hameenanttila, Jeffrey Kehl, Adi Habusha
  • Setting optimal space allocation policy for creating dependent snapshots to enhance application write performance and reduce resource usage
    Patent number: 9058120
    Abstract: In one embodiment, a system includes a network storage controller having logic adapted for receiving a request to duplicate at least a portion of a volume stored on the first disk array, logic adapted for creating at least one dependent volume on the first disk array, and logic adapted for duplicating the at least the portion of the volume to the at least one dependent volume on the first disk array to create a snapshot. Other systems, computer program products, and methods are described according to more embodiments.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Rahul M. Fiske, Subhojit Roy
  • Dynamic cache write policy
    Patent number: 9058282
    Abstract: A system, processor and method to monitor specific cache events and behavior based on established principles of quantized architectural vulnerability factor (AVF) through the use of a dynamic cache write policy controller. The output of the controller is then used to set the write back or write through mode policy for any given cache. This method can be used to change cache modes dynamically and does not require the system to be rebooted. The dynamic nature of the controller provides the capability of intelligently switching from reliability to performance mode and back as needed. This method eliminates the residency time of dirty lines in a cache, which increases soft errors (SER) resiliency of protected caches in the system and reduces detectable unrecoverable errors (DUE), while keeping implementation cost of hardware at a minimum.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: June 16, 2015
    Assignee: Intel Corporation
    Inventor: Arijit Biswas
  • Efficiently determining identical pieces of memory used by virtual machines
    Patent number: 9053053
    Abstract: Efficiently determining identical pieces of memory within a computer memory area, which is occupied by a virtual machine manager hosting multiple guests and the computer memory area being logically separated into memory pages of a unique size. Each guest is inspected for its structural characteristics by the virtual machine manager. The structural characteristics of each guest are compared by the virtual machine manager, wherein memory regions of guests having a similar structure are identified; and the identical memory pages are identified by the virtual machine manager by comparing hash values of memory pages located within memory regions of guests having a similar structure, wherein identical memory pages are determined by comparing hash values calculated over the contents of the memory pages.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: June 9, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Utz Bacher, Einar Lueck, Stefan Raspl, Thomas Spatzier
  • Compressed memory page selection based on a population count of a dataset
    Patent number: 9053018
    Abstract: A method, system, and computer program product for selecting memory pages for compression based on a population count associated with their datasets are disclosed. For example, a dataset stored in a memory page of an uncompressed memory is analyzed. Based on the analyzing, a population count associated with the dataset is identified. The population count is compared to at least one threshold. Based on the comparing, the memory page is selected or rejected for compression.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Nathan D. Fontenot, Jeffrey David George, Ryan P. Grimm, Joel H. Schopp, Michael T. Strosaker
  • System and method for cache content sharing
    Patent number: 9053033
    Abstract: A method, computer program product, and computing system for defining a first assigned cache portion within a cache system, wherein the first assigned cache portion is associated with a first machine. At least one additional assigned cache portion within the cache system is defined. The at least one additional assigned cache portion is associated with at least one additional machine. Content received by the first machine is written to the first assigned cache portion. After the occurrence of a reclassifying event, the first assigned cache portion is reclassified as a public cache portion that is added to an initial cache portion within the cache system. The public cache portion is associated with the first machine and the at least one additional machine.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: June 9, 2015
    Assignee: EMC Corporation
    Inventors: Philip Derbeko, Anat Eyal, Roy E. Clark
  • Circuit and method for initializing a computer system
    Patent number: 9046915
    Abstract: A circuit for use in a computing system including a bus interface unit and an autoload controller. The autoload controller has an input to receive an initialization signal. In response to receiving the initialization signal, the autoload controller searches for a signature using the bus interface unit and, in response to finding the signature at a signature address, loads a plurality of base addresses corresponding to a plurality of controllers from memory locations having a predetermined relationship to the address, and provides the plurality of base addresses to a control output thereof.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: June 2, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Xiao Gang Zheng, Ming L. So
  • Determining weight values for storage devices in a storage tier to use to select one of the storage devices to use as a target storage to which data from a source storage is migrated
    Patent number: 9047239
    Abstract: The present invention relates to a method, system, and computer program product for determining storage device weight values to use to select one of the storage devices to use as a target storage to which data from a source storage is migrated. A determination is made, for each of the storage devices, of static parameter values for static parameters comprising attributes of the storage device and dynamic parameter values for dynamic parameters providing device health information determined by accessing the storage device to determine operational conditions at the storage device. Storage device weight values are determined as a function of the static parameter values and the dynamic parameter values of the device. The determined storage device weight values are used to select one of the storage devices as the target storage to which data from the source storage is migrated.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bhooshan P. Kelkar, Sandeep R. Patil, Riyaz M. Shiraguppi, Prashant Sodhiya