Abstract: A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.

Abstract: The present disclosure provides a semiconductor memory device and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor memory device includes a substrate, a source structure, a laminated structure, a floating body, a trench region, a drain structure and a gate structure. The source structure is formed on the substrate. The laminated structure includes a nitride layer and an oxide layer that are alternately laminated on the source structure. The floating body is formed in the oxide layer, and a through hole is formed in the floating body along a lamination direction of the laminated structure. The trench region is formed inside the floating body, a through hole is also formed in the trench region along the lamination direction, and the trench region is in contact with the source structure.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a memory stack having a plurality of stairs. Each stair may include interleaved one or more conductor layers and one or more dielectric layers. Each of the stairs includes one of the conductor layers on a top surface of the stair, the one of the conductor layers having (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion exposed by the memory stack and in contact with the bottom portion. A lateral dimension of the top portion may be less than a lateral dimension of the bottom portion. An end of the top portion that may be facing away from the memory stack laterally exceeds the bottom portion by a distance.

Abstract: An organic light emitting display device includes a display panel including a display region where a plurality of pixels are disposed, a pad region including a bending region and a pad electrode region where pad electrodes are disposed, a polarizing layer disposed in the display region, and a lower protection film disposed on a lower surface of the display panel. The lower protection film includes a first and a second lower protection film pattern. The first lower protection film pattern is disposed in the display region, and the second lower protection film pattern in the pad electrode region such that a lower surface of the display panel in the bending region is exposed. The bending protection layer has an upper surface with a height that is less than a height of the polarizing layer, and is disposed in the bending region on the display panel.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

Abstract: A semiconductor device according to one embodiment includes a substrate, a stacked body including conductive layers and insulating layers alternately stacked on the substrate, and first contact plugs individually connected to the conductive layers on an end of the stacked body. The semiconductor device includes, on the substrate, a lower layer three-dimensional structure including any of a lower layer inclined structure continuously inclined upward with respect to a flat surface of the substrate, a lower layer stepped structure inclined upward in a stepwise manner with respect to the flat surface, and a lower layer composite stepped structure in which planes parallel to the flat surface and slopes inclined upward with respect to the flat surface are alternately continuous. At least some of terrace regions being connection regions to the first contact plugs on top surfaces of the conductive layers are located on the lower layer three-dimensional structure.

Abstract: A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel. Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion.

Abstract: A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

Abstract: A semiconductor device includes a stack including alternately stacked conductive films and insulating films, wherein the stack includes an opening penetrating the conductive films and the insulating films, and wherein the stack includes a rounded corner that is exposed to the opening. The semiconductor device also includes a first channel film formed in the opening and including a first curved surface surrounding the rounded corner. The semiconductor device further includes a conductive pad formed in the opening, and a second channel film interposed between the first curved surface of the first channel film and the conductive pad.

Abstract: The present invention includes a method for producing a filler-resin composite including (a) preparing a filler assembly in which a plurality of fillers are assembled, (b) impregnating at least one end in the thickness direction of the filler assembly with a first polymer soluble in liquid to produce a first polymer layer, (c) impregnating a portion of the filler assembly other than the one end in the thickness direction with a second polymer insoluble to the liquid to produce a second polymer layer, and (d) dissolving the first polymer layer impregnated at at least an end in the thickness direction of the filler assembly in the liquid to remove the first polymer layer.

Abstract: A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: The invention provides luminescent material comprising E1-wSc1-x-y-u-wMyZuA2wSi2-z-uGezAluO6:Crx, wherein: E comprises one or more of Li, Na, and K; M comprises one or more of Al, Ga, In, Tm, Yb, and Lu; Z comprises one or more of Ti, Zr, and Hf; A comprises one or more of Mg, Zn, and Ni; 0<x?0.25; 0?y?0.75; 0?z?2; 0?u?1; 0?w?1; x+y+u+w?1; and z+u?2.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a substrate and a stack structure in an insulating structure on the substrate. The stack structure includes alternating a plurality of conductor layers and a plurality of insulating layers. The 3D memory device further includes a source structure extending vertically through the alternating stack structure. The source structure includes at least one staggered portion along a respective sidewall. The 3D memory device further includes a channel structure and a support pillar each extending vertically through the alternating stack structure and a plurality of contact structures extending vertically through the insulating structure.

Abstract: A semiconductor wafer manufacturing method including: forming a plurality of trench capacitors at a main surface of a semiconductor wafer, wherein each of the plurality of trench capacitors is configured as unit cells that internally include unit trench capacitors, and wherein a length component in a predetermined direction of a layout pattern of trenches of the plurality of trench capacitors is made equivalent, within a fixed tolerance range, to a length component in a direction that intersects the predetermined direction.

Abstract: A hybridized image sensor includes a first die and a second die. The first die includes a first surface, a first plurality of conductive bumps fabricated on the first surface, and a first alignment feature fabricated on the first surface. The second die includes a second surface, a second plurality of conductive bumps fabricated on the second surface, and second alignment features fabricated on the second surface, wherein the first alignment features interact with the second alignment features to align the first plurality of conductive bumps with the second plurality of conductive bumps.

Abstract: A light emitting device includes: a light emitting element having a light emission peak wavelength in a range of 380 nm or more and 485 nm or less; a wavelength conversion member including a fluorescent material layer disposed on a light emission side of the light emitting element and containing a fluorescent material having a reflectance to light having a wavelength of 450 nm of 10% or less and a light emission peak wavelength in a range of 610 nm or more and 780 nm or less, and a dielectric multilayer film disposed on a light emission side of the fluorescent material layer.

Abstract: An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. A memory opening can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which may be optionally converted, partly or fully, into silicon nitride material portions. The semiconductor material portions and/or the silicon nitride material portions can be employed as discrete charge storage elements.

Abstract: According to one embodiment, a semiconductor device includes: a wiring layer including a first metallic film provided on an oxide film, a second metallic film provided on the first metallic film, and a polysilicon film provided on the second metallic film; and an element layer provided on the wiring layer and including semiconductor elements electrically connected to the first metallic film. Standard Gibbs energy of formation of a first metal included in the first metallic film is lower than that of a second metal included in the second metallic film.

Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.