Abstract: A data input device includes a first delay line, a second delay line, a detection circuit, and a processing circuit. The detection circuit is configured to detect whether a first output data output to a system circuit deviates from a first detection range and to generate a first deviation signal in response to that the detection circuit detects the first output data deviates from the first detection range. The processing circuit normally takes a first delayed data delayed by the first delay line as the first output data. In response to that the processing circuit receives that the first deviation signal representing the first delayed data deviates from the first detection range, the processing circuit takes a second delayed data delayed by the second delay line as the first output data after the second adjustable delay magnitude of the second delay line is adjusted.

Abstract: Aspects of the disclosure are directed to a cross-lane processing unit (XPU) for performing data-dependent operations across multiple data processing lanes of a processor. Rather than implementing operation-specific circuits for each data-dependent operation, the XPU can be configured to perform different operations in response to input signals configuring individual operations performed by processing cells and crossbars arranged as a stacked network in the XPU. Each processing cell can receive and process data across multiple data processing lanes. Aspects of the disclosure include configuring the XPU to use a vector sort network to perform a duplicate count eliminating the need to configure the XPU separately for sorting and duplicate counting.

Abstract: A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.

Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.

Abstract: Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.

Abstract: Techniques are provided for load balancing in a storage system using a storage system-driven host connectivity management process. For example, a load balancing process comprises monitoring a distribution of input/output (I/O) workload across resources of a storage system to detect for an occurrence of an I/O workload imbalance, generating updated connection information for a host system connected to the storage system, in response to detecting the occurrence of an I/O workload imbalance, and sending a request to the host system to discover the updated connection information for connecting to the storage system based on the updated connection information.

Abstract: Systems, methods, and apparatuses relating to 16-bit floating-point matrix dot product instructions are described.

Abstract: A method and apparatus for performing refactored multiply-and-accumulate operations is provided. A summing array includes a plurality of non-volatile memory elements arranged in columns. Each non-volatile memory element in the summing array is programmed to a high resistance state or a low resistance state based on weights of a neural network. The summing array is configured to generate a summed signal for each column based, at least in part, on a plurality of input signals. A multiplying array is coupled to the summing array, and includes a plurality of non-volatile memory elements. Each non-volatile memory element in the multiplying array is programmed to a different conductance level based on the weights of the neural network. The multiplying array is configured to generate an output signal based, at least in part, on the summed signals from the summing array.

Abstract: An electronic device may include a semiconductor memory structured to include a plurality of memory cells, wherein each of the plurality of memory cells may comprise: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple an electrical connection between the first electrode layer and the second electrode layer based on a magnitude of an applied voltage or an applied current with respect to a threshold magnitude, wherein the selection element layer has a dopant concentration profile which decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer.

Abstract: A method of enhanced hybrid quantum-classical computing mechanism for solving optimization problems is disclosed comprising altering a value of a configuration chromosome by storing an angle memory on a shared classical memory. The angle memory corresponds to a predefined configuration chromosome. The method then generates a state vector based on the angle memory and reinitializes a quantum circuit from the state vector. Subsequently, generating at least two most probable configuration chromosome from the reinitialized quantum circuit corresponding to a superposition of qubits in a position chromosome. Subsequently selecting one of the at least two most probable configuration chromosomes for each position chromosome after evaluation by a fitness function.

Abstract: A system and method for automatically identifying an anomalous pattern. The method encompasses receiving, a stream of data. The method further comprises determining, a monitoring metric for at least one of one or more dimensions and one or more groups of dimensions associated with the stream of data, at a target time and at a benchmark time period. Further the method comprises identifying, the monitoring metric at the target time as an outlier to the monitoring metric at the benchmark time period based at least on a threshold value. The method further comprises automatically identifying, the anomalous pattern based at least on said identification of the monitoring metric for at least one of the dimension(s) and the group(s) of dimensions at the target time as the outlier to the monitoring metric for at least one of the dimension(s) and the group(s) of dimensions at the benchmark time period.

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

Abstract: Aspects of the present disclosure provide an aligned storage strategy for stripes within a long vector for a vector processor, such that the extra computation needed to track strides between input stripes and output stripes may be eliminated. As a result, the stripe locations are located in a more predictable memory access pattern such that memory access bandwidth may be improved and the tendency for memory error may be reduced.

Abstract: A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.

Abstract: A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking active states for the regular expression and priorities for the active states by storing the active states of the regular expression in a plurality of priority FIFO memories in decreasing priority order. The system includes a capture engine operating in coordination with the regular expression engine to determine character(s) of the data stream that match the capture sub-expression based on the active state being tracked and decoding the capture entries of the capture table.

Abstract: Methods, systems, and computer-readable storage media for receiving, by a service mesh provisioned within a container orchestration system, a request from a client, determining, by the service mesh, a load balancing strategy that is to be applied for routing of the request within the heterogeneous cluster, and transmitting, by the service mesh, the request to a service within the heterogenous cluster, the service routing the request to a node for processing based on the load balancing strategy.

Abstract: One embodiment of a computer-implemented method for compiling a material graph into a set of instructions for execution within an execution unit includes receiving a first material graph having a plurality of nodes, wherein each node included in the plurality of nodes represents a different surface property of a material; parsing the material graph to generate an expression tree that includes one or more expressions for each node included in the plurality of nodes; and generating a set of byte code instructions corresponding to the material graph based on the expression tree, wherein the byte code instructions are executable by a plurality of processing cores included within the execution unit.

Abstract: An electronic device comprising circuitry configured to detect and read commands of a x-by-wire system (ECU1, ECU2, 25) from a communication bus (FLR) and to use the commands of the x-by-wire system (ECU1, ECU2, 25) as an input for an electronic gaming or simulation device (30).

Abstract: A multicore processor may include a plurality of cores including at least a first core and a second core, a shared peripheral comprising a plurality of interrupt register banks including at least a first interrupt register bank dedicated to the first core and a second interrupt register bank dedicated to the second core, and a plurality of communications bridges, including at least a first bridge interfaced between the first core and the shared peripheral and at least a second bridge interfaced between the second core and the shared peripheral. The first core may be configured to program the first interrupt register bank via the first bridge to configure the shared peripheral for access by the first core. The second core may be configured to program the second interrupt register bank via the second bridge to configure the shared peripheral for access by the second core.

Abstract: A method for creating a computer macro, the computer macro being executed on a computer, the computer including a processor, a display screen, a peripheral device, and a memory accessible by the processor, peripheral device, the method comprising: detecting, by a computer driver being at least partially resident in the memory, a computer program being at least partially resident in the memory to be executed in the computer; assigning, by the computer driver, at least one computer macro relating to the detected computer program to a key and/or button on the peripheral device; assigning, by the computer driver, a computer macro symbol relating to the assigned computer macro; storing, in the memory, the computer macro, the key and/or button on the peripheral device assigned to the computer macro and/or the assigned computer macro symbol; displaying, on the display screen via the computer driver, an on-screen-display, OSD, wherein the OSD is configured to display the assigned stored computer macro symbol and a re