Abstract: An application processor includes a memory interface and a memory controller. The memory interface is connected to a semiconductor memory device through first data input/output (I/O) pads and second data I/O pads. The memory controller exchanges data with the semiconductor memory device by controlling the memory interface. The memory interface includes a training circuit to perform duty training of first data signals and second data signals by adjusting a duty of each of the first data signals with respect to a first reference voltage and adjusting a duty of each of the second data signals with respect to a second reference voltage.

Abstract: Optimizing generalized transfers between storage systems including identifying, by a first storage system, a request to transfer source data from the first storage system to a second storage system, wherein the first storage system implements a first storage architecture and the second storage system implements a second storage architecture; identifying difference information between the source data that is stored on the first storage system using the first storage architecture and existing data that is stored on the second storage system using the second storage architecture; and transferring, in dependence upon the difference information, a subset of the source data from the first storage system to the second storage system.

Abstract: Dock-connected peripherals can be enumerated in a preferred order. When a client computing device is connected to a dock, a dock service can report peripherals connected to the dock one-by-one to ensure that each peripheral is enumerated in the preferred order. The preferred order can be defined based on a user's usage of the peripherals including an order of usage, a usage frequency, and a purpose.

Abstract: Techniques of handling interrupt escalation are implemented in hardware. In at least one embodiment, an interrupt presentation controller (IPC) receives an event notification message requesting an interrupt, specifying an interrupt priority, and referencing a virtual processor (VP) thread. The IPC determines whether the VP thread matches any interruptible VP thread. If not, the IPC conditionally escalates the interrupt requested by the event notification message. Conditionally escalating the interrupt includes determining whether or not the interrupt priority is greater than the operating priority of any interruptible VP thread. If so, the IPC initiates escalation of the interrupt requested by the event notification message to a next higher software stack level by issuing an escalate message. If not, the IPC refrains from escalating the interrupt requested by the event notification message.

Abstract: Remote storage management using linked directory objects that are persisted in one of a plurality of remote storages. A first directory object is generated to record addresses of a plurality of fragments of data, relational to identifiers of the plurality of fragments of data. In response to determining that an address of at least one of the plurality of fragments is changed, a second directory object is generated to record a changed address of the at least one fragment. An address of the second directory object is then recorded in the first directory object, associating the address of the second directory object with the previous address of the at least one fragment stored in the first directory object.

Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

Abstract: A synchronizer that can generate pipeline (e.g., FIFO, LIFO) status in a single step without intermediate synchronization. The status can be an indicator of whether a pipeline is full, empty, almost full, or almost empty. The synchronizer (also referred to as a double-sync or ripple-based pipeline status synchronizer) can be used with any kind of clock crossing pipeline and all kinds of pointer encodings. The double-sync and ripple-based pipeline status synchronizers eliminate costly validation and semi-manual timing closure, suggests better performance and testability, and have lower area and power.

Abstract: A memory device is configured to communicate with a plurality of host devices, through an interconnect, and includes a memory including a plurality of memory regions that includes a first memory region that is assigned to a first host device and a second memory region that is assigned to a second host device. The memory device further includes a direct memory access (DMA) engine configured to, based on a request from the first host device, the request including a copy command to copy data that is stored in the first memory region to the second memory region, read the stored data from the first memory region, and write the read data to the second memory region without outputting the read data to the interconnect.

Abstract: In a control system including one or more control nodes and one or more I/O nodes connected to one or more devices and communicable with the control nodes, the control nodes execute at least one control program on a first OS, and the I/O nodes execute at least one I/O program on a second OS with higher punctuality. The control program generates a control command based on state control set in advance for the device and transmits the control command to the I/O node. The I/O program stores the control command received from the control node in a storage unit, and executes processing related to the device according to the control command stored in the storage unit.

Abstract: Disclosed herein is an apparatus that includes a memory, a processor, and a rectangular waveguide coupled to the memory and the processor so that the memory and the processor communicate with each other via the rectangular waveguide.

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

Abstract: Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.

Abstract: A data storage library system includes a data storage library, at least one environmental conditioning unit, at least one data storage drive retained within the data storage library, and at least one access door for providing access to an interior portion of the data storage library. The system also includes a library controller, wherein the library controller is configured to initiate a service mode prior to and during a service procedure performed within the data storage library, and further wherein at least one operational state within the at least one data storage drive is changed during the service mode. The change in the at least one operational state may be, for example, an increase in temperature within the at least one data storage drive, or the insertion of a data storage cartridge into the at least one data storage drive during the service mode.

Abstract: Unified systems and methods for interchip and intrachip node communication are disclosed. In one aspect, a single unified low-speed bus is provided that connects each of the chips within a computing device. The chips couple to the bus through a physical layer interface and associated gateway. The gateway includes memory that stores a status table summarizing statuses for every node in the interface fabric. As nodes experience state changes, the nodes provide updates to associated local gateways. The local gateways then message, using a scout message, remote gateways with information relating to the state changes. When a first node is preparing a signal to a second node, the first node checks the status table at the associated local gateway to determine a current status for the second node. Based on the status of the second node, the first node may send the message or take other appropriate action.

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

Abstract: Methods, apparatuses, and computer-readable media for streaming arbitrarily large amounts of data through computational storage programs of a computational storage device. A computational storage device comprises a storage media, a computational storage processor, and a controller. A firmware of the controller comprises a plurality of streaming drivers, each associated with a data source or data destination of the storage device. The firmware further comprises a buffer abstraction layer operable to read data from a data source through an associated ingress streaming driver of the plurality of streaming drivers to provide a source data stream for a computational storage program executing on the computational storage processor. The buffer abstraction layer is further operable to receive a destination data stream from the computational storage program and write data to a data destination through an associated egress streaming driver of the plurality of streaming drivers.

Abstract: The disclosure provides an information processing device and method. The information processing device includes a storage module a storage module configured to acquire information data, wherein the information data including at least one key feature and the storage module pre-storing true confidence corresponding to the key feature; an operational circuit configured to determine predicted confidence corresponding to the key feature according to the information data and judge whether the predicted confidence of the key feature exceeds a preset threshold value range of the true confidence corresponding to the key feature or not; a controlling circuit configured to control the storage module to modify the key feature or send out a modification signal to the outside when the predicted confidence exceeds the preset threshold value of the true confidence. The information processing device of the disclosure can automatically correct and modify handwriting, text, image or video actions instead of artificial method.

Abstract: A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.

Abstract: A storage device and method of controlling a storage device are disclosed. The storage device includes a host, a logic die, and a high bandwidth memory stack including a memory die. A computation lookup table is stored on a memory array of the memory die. The host sends a command to perform an operation utilizing a kernel and a plurality of input feature maps, includes finding the product of a weight of the kernel and values of multiple input feature maps. The computation lookup table includes a row corresponding to a weight of the kernel, and a column corresponding to a value of the input feature maps. A result value stored at a position corresponding to a row and a column is the product of the weight corresponding to the row and the value corresponding to the column.

Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.