Abstract: Techniques are provided for generating host connectivity plans with load balancing and resiliency. One method comprises obtaining a number of storage system target ports needed for a given host; identifying available target ports in the storage system and an input-output (IO) target component associated with each available target port; and calculating the host connectivity plan until the host connectivity plan includes the obtained number of target ports by: (i) selecting at least one IO target component not already in the host connectivity plan that satisfies a resiliency policy and/or a load balancing policy; (ii) selecting at least one target port associated with the selected at least one IO target component and (iii) adding the selected at least one target port to the host connectivity plan. The resiliency policy may require connectivity without a single point of failure. The load balancing policy may specify that the IO target components serve a substantially equal IO load.

Abstract: A single use probe, sterilizable by irradiation, for a single use component for use in a biopharmaceutical process, comprises at least one sensor relevant for the biopharmaceutical process, an RFID tag and a memory rewritable in principle, in which data with respect to an integrity check of the single use probe are stored. A method for quality assurance of such a single use probe comprises: providing the probe with an RFID tag and a memory rewritable in principle, in particular a FeRAM memory as part of the RFID tag; defining a measurement-principle-specific quality parameter of the single use probe; defining a tolerance value for the parameter; performing an integrity check of the probe by first determining and writing into the memory values of the defined quality parameter before sterilization of the probe by irradiation; determining the values of the defined quality parameter after irradiation; and comparing the values of the quality parameter determined before radiation to those determined after.

Abstract: An information handling system may include a processor and a storage subsystem. The storage subsystem may include a non-expander backplane, a first plurality of storage resources coupled to the processor via the non-expander backplane, and a second plurality of storage resources coupled to the processor via a communication path that does not include the non-expander backplane. The information handling system may be configured to provide slot numbers for the storage resources according to a numbering scheme in which a storage resource from the first plurality of storage resources and a storage resource from the second plurality of storage resources have the same slot number.

Abstract: A storage device is disclosed. The storage device may include compute engines. The compute engines may include storage for data, a storage processing unit to manage writing data to the storage and reading data from the storage, a data processing unit to perform some functions on the data, and an accelerator to perform other functions on the data. An Ethernet component may receive a request at the storage device from a host over a network. A data processing coordinator may process the request using a compute engine.

Abstract: Provided is a semiconductor device and a semiconductor system. A semiconductor device can include a command priority policy manager circuit which generates command priority policy information including a command priority compliance policy for a command directed to a device. A host interface circuit can be coupled to the command priority policy manager circuit to receive the command priority policy information from the command priority policy manager circuit, where the host interface circuit operable to transmit the command priority policy information via an electrical interface to the device.

Abstract: A data storage library system includes a data storage library, at least one environmental conditioning unit, at least one data storage drive retained within the data storage library, and at least one access door for providing access to an interior portion of the data storage library. The system also includes a library controller, wherein the library controller is configured to initiate a service mode prior to and during a service procedure performed within the data storage library, and further wherein at least one operational state within the at least one data storage drive is changed during the service mode. The change in the at least one operational state may be, for example, an increase in temperature within the at least one data storage drive, or the insertion of a data storage cartridge into the at least one data storage drive during the service mode.

Abstract: Disclosed in some examples are methods, systems, devices, memory controllers, memory dies, memory devices, and machine-readable mediums that allow for efficient updating of software instructions of the memory die. In some examples, the controller of the memory device may cause the software instructions of one or more memory dies to be updated by causing the page buffers of the one or more memory dies to be loaded with updated software instructions and subsequently issuing a command to the memory die to update the software instructions from the page buffer.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on one of a first access protocol and a second access protocol that is different from the first access protocol, and select between the first access protocol and the second access protocol at runtime based on a user configurable parameter. Other embodiments are disclosed and claimed.

Abstract: Examples include a method of switching a packet by a virtual switch by receiving a system call to transmit a packet from a first application running in a first container on a first core, determining a destination for the packet, obtaining a buffer in an application memory space of the destination, copying the packet to the destination application memory space, and writing an entry for the packet to a queue assigned to the destination, the destination queue being in a queue manager. The packet may then be obtained by an entity at the destination.

Abstract: An information handling system, method, and processor that detects a store instruction for data in a processor where the store instruction is a reliable indicator of a future load for the data; in response to detecting the store instruction, sends a prefetch request to memory for an entire cache line containing the data referenced in the store instruction, and preferably only the single cache line containing the data; and receives, in response to the prefetch request, the entire cache line containing the data referenced in the store instruction.

Abstract: The present invention provides a data transmission system and resource allocation method thereof. The data transmission system is configured to: retrieve master device resource information and slave device performance information; based on a neural network model, determine at least one arbiter setting parameter according to the master device resource information and the slave device performance information; and determine resource allocation setting of at least one master device according to the at least one arbiter setting parameter.

Abstract: Disclosed herein are techniques for performing multi-layer neural network processing for multiple contexts. In one embodiment, a computing engine is set in a first configuration to implement a second layer of a neural network and to process first data related to a first context to generate first context second layer output. The computing engine can be switched from the first configuration to a second configuration to implement a first layer of the neural network. The computing engine can be used to process second data related to a second context to generate second context first layer output. The computing engine can be set to a third configuration to implement a third layer of the neural network to process the first context second layer output and the second context first layer output to generate a first processing result of the first context and a second processing result of the second context.

Abstract: There is provided a neural processing unit (NPU), including a primary processing node containing primary control registers and processing circuitry configured to write control data to the primary control registers, and multiple secondary processing nodes each having respective secondary control registers and being configured to process data in accordance with control data stored by the respective secondary control registers. The NPU also includes a bus interface for transmitting data between the primary processing node and the plurality of secondary processing nodes. The primary processing node is configured to transmit first control data to a given secondary control register of each of the plurality of secondary processing nodes.

Abstract: A method may include determining, with a queue availability module, that an entry is available in a queue, asserting a bit in a register based on determining that an entry is available in the queue, determining, with a processor, that the bit is asserted, and processing, with the processor, the entry in the queue based on determining that the bit is asserted. The method may further include storing the register in a tightly coupled memory associated with the processor. The method may further include storing the queue in the tightly coupled memory. The method may further include determining, with the queue availability module, that an entry is available in a second queue, and asserting a second bit in the register based on determining that an entry is available in the second queue. The method may further include finding the first bit in the register using a find first instruction.

Abstract: Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.

Abstract: A group of transistors is configured to drive a bus at time slots, to express data on the bus. The group of transistors dissipates an amount of electrical energy when driving the bus to a logic level opposite to a logic level present on the bus in an immediate preceding time slot. The group of transistors is arranged to dump another amount of electrical energy. Dumping of the other amount of electrical energy is responsive to driving the bus to a logic level that is the same as present on the bus in an immediate preceding time slot. The dumped amount of electrical energy is equivalent to the amount of energy dissipated by the transistors when transitioning the bus to a different logic level. Other aspects are also described.

Abstract: Techniques for synchronizing operations of execution engines of an integrated circuit device are disclosed. A description of a plurality of operations to be performed by the execution engines may be obtained. The plurality of operations may be connected through a plurality of edges. A dependency vector may be generated for each operation of the plurality of operations. The dependency vector of a corresponding operation may include a set of values that are calculated based on the set of values of one or more dependency vectors calculated for one or more immediately preceding operations of the plurality of operations. An event register of a plurality of event registers may be assigned, for each edge of one or more of the plurality of edges, to the corresponding edge based on the dependency vector generated for a start operation associated with the corresponding edge.

Abstract: A system and method for generating a modified input/output (I/O) device policy for multiple users. A method includes generating a modified policy based on a first policy and a second policy, wherein the modified policy is generated when a first user and a second user are located within a predetermined distance of each other, wherein the first policy is generated for the first user based on a first dataset including data related to the first user with respect to at least one I/O device, wherein the second policy is generated for the second user based on data related to the at least one I/O device; and executing at least one plan based on the modified policy, wherein executing the at least one plan further comprises causing the at least one I/O device to output a signal for causing at least one action by an external system.

Abstract: A technique for user notification involves receiving an event notification related to an event associated with user notification by a user; providing the event notification from a stored array to a process executed by a processor; using the event notification as a first title used for the process; providing a second title from the stored array to the process; and using the second title to identify the process to the user.

Abstract: A computer device including an integrated input device is provided. The integrated input device includes a positive disconnect system including a display of an open connection to the integrated input device when the integrated input device is deactivated. The open connection comprises a visible metal trace on a line coupling the integrated input device to the computer device.