Abstract: A method of manufacturing a current collector for use in a capacitor (e.g., a DEL capacitor) having an aqueous or non-aqueous electrolyte, such as an aqueous sulfuric acid electrolyte. The conductive basis of the current collector is preferably, but not necessarily, comprised of lead or a lead alloy. The portion of the conductive basis that will be in contact with the electrolyte is provided with a protective layer that is created by deposition of one or more layers of one or more protective coating materials thereto. Each protective coating material is comprised of at least a conductive carbon powder and a polymer binder that is resistant to the electrolyte. Preferably, but not essentially, the protective coating material(s) are applied to the conductive basis in the form of a paste, which is subsequently subjected to a solvent evaporation step and a thermal treatment step.

Abstract: A transistor having a source with higher resistance than its drain is optimal as a pull-up device in a storage circuit. The transistor has a source region having a source implant having a source resistance. The source region is not salicided. A control electrode region is adjacent the source region for controlling electrical conduction of the transistor. A drain region is adjacent the control electrode region and opposite the source region. The drain region has a drain implant that is salicided and has a drain resistance. The source resistance is more than the drain resistance because the source region having a physical property that differs from the drain region.

Abstract: A method of manufacturing partially light transparent thin film solar cells generally includes forming a solar cell structure stack and forming multiple openings through the solar cell structure stack. The solar cell structure stack includes a flexible foil substrate, a contact layer formed over the flexible foil substrate, a Group IBIIIAVIA absorber layer formed over the contact layer and a transparent conductive layer formed over the Group IBIIIAVIA absorber layer. A terminal structure including at least one busbar and a plurality of conductive finger patterns is deposited onto a top surface of the transparent conductive layer forming a semi-transparent solar cell.

Abstract: Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a metal source chemical, a silicon source chemical and an oxidizing agent. In preferred embodiments, an alkyl amide metal compound and a silicon halide compound are used. Methods according to preferred embodiments can be used to form hafnium silicate and zirconium silicate films with substantially uniform film coverages on substrate surfaces comprising high aspect ratio features (e.g., vias and/or trenches).

Abstract: A method for manufacturing a thin film transistor (TFT) is disclosed. The method is achieved by forming and defining a source and a drain of a thin film transistor through two lithographic processes cycles so that the channel length (L) of the thin film transistor can be reduced to 1.5 to 4.0 ?m. Besides, the Ion current of the thin film transistor is increased as the channel length (L) is decreased. Therefore, the component area of the thin film transistor is decreased as the channel width (W) is decreased. Thus, the aperture ratio of the TFT-LCD can be increased due to the decreased component area of the thin film transistor.

Abstract: A siloxane polymer composition includes an organic solvent in an amount of about 93 percent by weight to about 98 percent by weight, based on a total weight of the siloxane polymer composition, and a siloxane complex in an amount of about 2 percent by weight to about 7 percent by weight, based on the total weight of the siloxane polymer composition, the siloxane complex including a siloxane polymer with an introduced carboxylic acid and being represented by Formula 1 below, wherein each of R1, R2 R3, and R4 independently represents H, OH, CH3, C2H5, C3H7, C4H9 or C5H11, R? represents CH2, C2H4, C3H6, C4H8, C5H10 or C6H12, and n represents a positive integer so the siloxane polymer of the siloxane complex has a number average molecular weight of about 4,000 to about 5,000.

Abstract: Embodiments of the invention describe TiN deposition methods suitable for high volume manufacturing of semiconductor devices on large patterned substrates (wafers). One embodiment describes a chemical vapor deposition (CVD) process using high gas flow rate of a tetrakis(ethylmethylamino) titanium (TEMAT) precursor vapor along with an inert carrier gas at a low process chamber pressure that provides high deposition rate of conformal TiN films with good step coverage in surface reaction limited regime. Other embodiments describe cyclical TiN deposition methods using TEMAT precursor vapor and a nitrogen precursor.

Abstract: A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and method to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect.

Abstract: This invention proposes a method for making very low threshold voltage (Vt) metal-gate/high-? CMOSFETs using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with VLSI. At 1.2 nm equivalent-oxide thickness (EOT), good effective work-function of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85° C. bias-temperature-instability <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.

Abstract: An integrated circuit having a metal interconnect layer, and also having a conductive line and a boundary defined with a uniform distance from the conductive line that defines a “keep out” distance between the boundary and the conductive line. A set of first fill elements are uniformly arranged along the boundary outside of the “keep out” distance, and a set of second fill elements further from the conductive line than the first fill elements are arranged in a pattern that would be uniform, but for having some fill elements missing from the pattern.

Abstract: A method includes providing a wafer having a first die and a scribe grid, where the first die has die circuitry and a bond pad electrically connected to the die circuitry, and where the scribe grid has a scribe grid pad electrically connected to the die circuitry. The method further includes accessing the scribe grid pad to stimulate the die circuitry. A wafer includes a first die. The first die includes die circuitry, a plurality of conductive layers, and a bond pad electrically connected to the die circuitry via at least one conductive layer of the plurality of conductive layers. The wafer includes a scribe grid having a scribe grid pad, and an interconnect electrically connecting the scribe grid pad to the die circuitry. The plurality of die of the wafer can then be singulated, and at least one of the singulated die can be packaged.

Abstract: A process for fabricating a pendulous accelerometer, including the steps of: providing a first substrate having a top planar surface, etching a portion of the first substrate to a first predetermined depth from the top planar surface to form a plurality of first protrusions, providing a second substrate, etching a portion of the second substrate to a second predetermined depth to form a plurality of second protrusions, bonding planar surfaces of the first protrusions to planar surfaces of the second protrusions, and etching a portion of the first substrate from an opposite side of the first substrate to a third predetermined depth equal to or greater than the difference between the total thickness of the first substrate and the first predetermined depth to form a freely rotatable sensing plate that includes a substantially hollow proof mass.

Abstract: A method of making a bonded intermediate substrate includes forming a weak interface in a GaN source substrate by implanting ions into an N-terminated surface of the GaN source substrate, bonding the N-terminated surface of the GaN source substrate to a handle substrate, and exfoliating a thin GaN single crystal layer from the source substrate such that the thin GaN exfoliated single crystal layer remains bonded to the handle substrate and a Ga-terminated surface of the thin GaN single crystal layer is exposed. The method further includes depositing a capping layer directly onto the exposed surface of the thin GaN single crystal layer, and annealing the thin GaN single crystal layer in a nitrogen containing atmosphere after depositing the capping layer. The in-plane strain present in the thin GaN single crystal layer after the annealing is reduced relative to an in-plane strain present in said layer prior to the annealing.

Abstract: In a method of manufacturing a semiconductor device, a conductive layer pattern may be formed on a substrate. An oxide layer may be formed on the substrate to cover the conductive layer pattern. A diffusion barrier layer may be formed by treating the oxide layer to increase an energy required for a diffusion of impurities. An impurity region may be formed on the substrate by implanting impurities into the conductive layer pattern and a portion of the substrate adjacent to the conductive layer pattern, through the diffusion barrier. The impurities in the conductive layer pattern and the impurity region may be prevented or reduced from diffusing, and therefore, the semiconductor device may have improved performance.

Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.

Abstract: A method for forming a median crack and an apparatus for forming a median crack are provided, where the formation of a deep, straight median crack is possible, and an excellent broken surface of a brittle substrate can be gained as a result of breaking.

Abstract: A method for designing a photomask pattern is provided. First, all line ends of object patterns are determined with reference to layout data. Then, object patterns, front edge portions, and joints, which are aligned on the same line extending along the Y-axis, are connected to form first reticle data. Reticle pattern data having data representing binding portions serving as light blocking portions is formed. The front edge portions being adjacent to each other and aligned in the X-axis are connected and adjacent joints being aligned in the same manner as the front edge portions are also connected to form second reticle data. Then, portions are provided at central regions between the binding portions so as to connect the adjacent binding portions including the front edge portions and the joints. Then, reticle data having data representing the binding portions serving as transparent patterns is formed.

Abstract: A method of forming copper-comprising conductive lines in the fabrication of integrated circuitry includes depositing damascene material over a substrate. Line trenches are formed into the damascene material. Copper-comprising material is electrochemically deposited over the damascene material. The copper-comprising material is removed and the damascene material is exposed, and individual copper-comprising conductive lines are formed within individual of the line trenches. The damascene material is removed selectively relative to the conductive copper-comprising material. Dielectric material is deposited laterally between adjacent of the individual copper-comprising conductive lines. The deposited dielectric material is received against sidewalls of the individual copper-comprising conductive lines. A void is received laterally between immediately adjacent of the individual copper-comprising conductive lines within the deposited dielectric material. Other embodiments are contemplated.

Abstract: A metal interconnect structure formed over a substrate in an integrated circuit that traverses a scribe-line boundary between a first die and a second die includes at least one metal interconnect line that traverses the scribe-line boundary. A switch is coupled between the at least one metal interconnect line and the substrate, the switch having a control element coupled to a scribe-cut control line. The control line turns the switch on if the two dice are separated into individual dice and turns the switch off if the two dice are to remain physically connected so that the interconnect line may be used to make connections between circuits on the two dice.

Abstract: A method of cleaning a semiconductor substrate conductive layer surface that can remove a residual organic material and a natural oxide satisfactorily and does not adversely affect a k value without damaging the side-wall insulation film of a via hole. A semiconductor device, including insulation films formed on the surface of a conductive layer of a semiconductor substrate and a via hole formed in an insulation film to partly expose the conductive layer, is carried into a reaction vessel, plasma including hydrogen is generated in the reaction vessel to clean the surface of the conductive layer at the bottom of the via hole, a residual organic material is decomposed and removed by ashing, and a copper oxide film on the surface of the conductive layer is reduced to Cu.