Abstract: Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.

Abstract: A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and through-hole vias (THV) provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die.

Abstract: An adhesive film includes an amine curing agent and a phenolic curing agent, and has a ratio of a storage modulus at 170° C. after 80% or more curing to a storage modulus at 40° C. before curing in the range of about 1.5 to about 3.0.

Abstract: A semiconductor device includes a semiconductor substrate having opposed main and back surfaces; first and second electrodes in a device region of the substrate, and spaced apart from each other; a metal film on the main surface and joined to the second electrode; an air gap between part of the main surface and the metal film, enveloping the first electrode, and having an opening; a cured resin closing the opening; a liquid repellent film increasing contact angle of the resin, relative to contact angles on the substrate and the metal film; a first metal film joined to the metal film, covering the metal film and the cured resin, and joined to an outer peripheral region of the substrate, at a periphery of the device region; and a second metal film on the back surface and connected to the first electrode through a via hole penetrating the substrate.

Abstract: A disclosed method of depositing a silicon film on a substrate mounted on a turntable and can pass by rotation through a first process area and a second process area, which are separately arranged along a peripheral direction in a cylindrical chamber set to have a first temperature capable of cutting a Si—H bond includes a molecular layer deposition step of supplying a Si2H6 gas set to have a second temperature less than the first temperature when the substrate passes through the first process area thereby forming a SiH3 molecular layer on a surface of the substrate, and a hydrogen desorption step of causing the substrate, on a surface of which the SiH3 molecular layer is formed, to pass through the second process area maintained to have the first temperature thereby cutting the Si—H bond and leaving only a silicon atomic layer on the surface of the substrate.

Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Abstract: An image sensor pixel array includes a photoelectric conversion unit comprising a photoelectron accumulation region of n-type in a substrate of p-type and vertically below a gate electrode of a transistor. A light guide transmits a light of red or green or yellow color across the gate electrode to the photoelectron accumulation region. The gate electrode may be made thinner by a wet etch. An etchant for thinning the gate electrode may be introduced through an opening in an insulating film on the substrate. The light guide may be formed in the opening after the thinning. An anti-reflection stack may be formed at a bottom of the opening prior to forming the light guide.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.

Abstract: A method and a semiconductor device for incorporating defect mitigation structures are provided. The semiconductor device comprises a substrate, a defect mitigation structure comprising a combination of layers of doped or undoped group IV alloys and metal or non-metal nitrides disposed over the substrate, and a device active layer disposed over the defect mitigation structure. The defect mitigation structure is fabricated by depositing one or more defect mitigation layers comprising a substrate nucleation layer disposed over the substrate, a substrate intermediate layer disposed over the substrate nucleation layer, a substrate top layer disposed over the substrate intermediate layer, a device nucleation layer disposed over the substrate top layer, a device intermediate layer disposed over the device nucleation layer, and a device top layer disposed over the device intermediate layer.

Abstract: An epitaxial structure includes a patterned epitaxial growth surface defining a plurality of grooves. A graphene layer covers the patterned epitaxial growth surface. An epitaxial layer is formed on the patterned epitaxial growth surface, wherein a first part of the graphene layer is sandwiched between the substrate, and a second part of the graphene layer is embedded into the epitaxial layer.

Abstract: A method for making an epitaxial structure includes following steps. A substrate having an epitaxial growth surface is provided. A first epitaxial layer is epitaxially grown on the epitaxial growth surface. A graphene layer is applied on the first epitaxial layer. A second epitaxial layer is epitaxially grown on the first epitaxial layer.

Abstract: A highly reliable semiconductor device is provided. Over an oxide semiconductor layer in which a channel is formed, an insulating layer including the oxide semiconductor material having a higher insulating property than an oxide semiconductor layer is formed. A material which contains an element M and is represented by a chemical formula InMZnOX (X>0) or an oxide material which contains an element M1 and an element M2 and is represented by a chemical formula InM1XM2(1?X)ZnO (0<X<1+? where ? is less than 0.3 and (1?X)>0) is used as the oxide semiconductor material having a high insulating property. Ti, Zr, Hf, Ge, Ce, or Y is used as the element M and the element M2, for example. Ga is used as the element M1, for example.

Abstract: A method of forming a fluorine-free tungsten diffusion barrier layer having a reduced resistivity, and a semiconductor device, and method for forming such semiconductor device, using the fluorine-free tungsten diffusion barrier layer.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type involves forming a first region having a second conductivity type within the doped region, forming a body region having the first conductivity type overlying the first region, and forming a drift region having the second conductivity type within the doped region, wherein at least a portion of the drift region abuts at least a portion of the first region. In one embodiment, the dopant concentration of the first region is less than the dopant concentration of the body region and different from the dopant concentration of the drift region.

Abstract: A nonvolatile semiconductor memory device a first memory cell array layer, a first insulation layer formed on top of the first memory cell array layer, a second memory cell array layer formed on the first insulation layer, and a control gate. The first and second memory cell array layers have first and second NAND cell units provided with multiple first and second memory cells connected in series in a first direction and the first and second selection gates connected at both ends of the multiple first and second memory cells. The control gate is formed via an insulation layer between gates of the memory cells on both sides thereof in the first direction, and extends in the second direction perpendicular to the first direction.

Abstract: A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal.

Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.

Abstract: A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner.

Abstract: A method for forming a conformal, homogeneous dielectric film includes: forming a conformal dielectric film in trenches and/or holes of a substrate by cyclic deposition using a gas containing a silicon and a carbon, nitrogen, halogen, hydrogen, and/or oxygen, in the absence of a porogen gas; and heat-treating the conformal dielectric film and continuing the heat-treatment beyond a point where substantially all unwanted carbons are removed from the film and further continuing the heat-treatment to render substantially homogeneous film properties of a portion of the film deposited on side walls of the trenches and/or holes and a portion of the film deposited on top and bottom surfaces of the trenches and/or holes.

Abstract: A semiconductor package substrate including a substrate body having a front surface configured for mounting a semiconductor chip on the front surface and a rear surface facing the front surface and comprising a window passing through the front and rear surfaces, the window having one or more surfaces inclined from the front surface toward the rear surface; and a conductive pattern arranged along an inclined surface of the window so as to extend from the front surface to the rear surface of the substrate body.