Abstract: A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of the substrate. The external connection terminals are formed by sequentially forming an electroless nickel plating layer, an electroless gold plating layer, and an electrolytic gold plating layer on a terminal portion formed on a surface of the substrate.

Abstract: The invention relates to a method 10 for forming a multi-level surface on a substrate 2, wherein said surface comprises areas of different wettability, the method comprising the step (A, B) of applying a multi-level stamp to the substrate for forming the multi-level surface, said multi-level stamp having different structural regions 1a arranged along the multi-level surface for locally altering wettability properties of at least a portion of a level of the multi-level surface 2a, 2b. The invention further relates to a semiconductor device and a method for manufacturing a semiconductor device.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of an electrical property as a function of cathode voltage used during a sputtering process. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials, be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).

Abstract: Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate electrodes with sidewall spacers, the sacrificial gate electrodes with sidewall spacers being separated by, at least in part, a first dielectric material, wherein the first dielectric material is recessed below upper surfaces of the sacrificial gate electrodes, and the upper surfaces of the sacrificial gate electrodes are exposed and coplanar; conformally depositing a protective film over the sacrificial gate electrodes, the sidewall spacers, and the first dielectric material; providing a second dielectric material over the protective film, and planarizing the second dielectric material, stopping on and exposing the protective film over the sacrificial gate electrodes; and opening the protective film over the sacrificial gate electrodes to facilitate performing a replacement gate process.

Abstract: A field-effect transistor is integrated in a chip of semiconductor material of a first type of conductivity, which has a first main surface and a second main surface, opposite to each other. The transistor includes a plurality of body regions of a second type of conductivity, each one extending from the second main surface in the chip. A plurality of drain columns of the second type of conductivity are provided, each one extending from a body region towards the first main surface, at a pre-defined distance from the first main surface. A plurality of drain columns are defined in the chip, each one extending longitudinally between a pair of adjacent drain columns. The transistor includes a plurality of source regions of the first type of conductivity, each one of them extending from the second main surface in a body region; a plurality of channel areas are defined, each one in a body region between a source region of the body region and each drain channel adjacent to the body region.

Abstract: A nitride-based semiconductor light emitting device includes an anti-bowing layer having a composition of AlxGa1-xN (0.01?x?0.04), and a light emitting structure formed on the anti-bowing layer and including a first conductivity-type nitride semiconductor layer, an active layer, and a second conductivity-type nitride semiconductor layer.

Abstract: A semiconductor device according to the present embodiment includes a diamond substrate having a surface plane inclined from a (100) plane in a range of 10 degrees to 40 degrees in a direction of <011>±10 degrees, and an n-type diamond semiconductor layer containing phosphorus (P) and formed above the surface plane described above.

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; an electrode in a device region on the main surface; a metal wiring on the main surface and having a first end connected to the electrode; an electrode pad outside the device region and spaced from the metal wiring; an air gap between the main surface and an air gap forming film on the main surface, enveloping the first end of the metal wiring and the electrode, and having a first opening; a resin closing the first opening and covering a second end of the metal wiring; a liquid repellent film facing the air gap and increasing contact angle of the resin, when liquid, relative to contact angles on the semiconductor substrate and the air gap forming film; and a metal film connecting the metal wiring to the electrode pad through a second opening located in the resin.

Abstract: A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar.

Abstract: A light emitting device including a light emitting structure including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, a first electrode disposed on the first conductive semiconductor layer, a conductive layer disposed on the second conductive semiconductor layer, a second electrode disposed on the conductive layer, a channel layer directly contacts with the light emitting structure and disposed at an adjacent region of the second electrode, a support substrate disposed on the channel layer, and wherein the conductive layer is separated into at least two unit conductive layers.

Abstract: A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third diffusion layers are the same.

Abstract: A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging.

Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.

Abstract: Methods of forming titanium-containing layers on substrates are disclosed. In the disclosed methods, the vapor of a precursor compound having the formula Ti(Me5Cp)(OR)3, wherein R is selected from methyl, ethyl, or isopropyl is provided. The vapor is reacted with the substrate according to an atomic layer deposition process to form a titanium-containing complex on the surface of the substrate.

Abstract: A multi-chip package includes a lower substrate; at least two semiconductor chips stacked over the lower substrate and each defined with a via hole; an upper substrate coupled to a semiconductor chip positioned uppermost among the semiconductor chips; a light emitting part coupled to the lower substrate corresponding to the via hole; an electrowetting liquid lens coupled to a lower surface of the upper substrate for receiving a signal transferred from the light emitting part through the via hole; a light receiving part coupled to a sidewall of the via hole of each semiconductor chip configured to receive a signal from the electrowetting liquid lens.

Abstract: Described herein are microelectronic packages including a plurality of bonding fingers and multiple integrated circuit chips, at least one integrated circuit chip being mounted onto the bonding fingers. According to various embodiments of the present invention, mounting the integrated circuit chip onto the bonding fingers may reduce the pin-out count by allowing multiple integrated circuit chips to be interconnected within the same microelectronic package. Other embodiments may be described and claimed.

Abstract: In one embodiment, a method of forming a semiconductor package includes placing a first die and a second die over a carrier. At least one of the first and the second dies are covered with an encapsulation material to form an encapsulant having a top surface and an opposite bottom surface. The encapsulant is thinned from the bottom surface to expose a first surface of the first die without exposing the second die. The exposed first surface of the first die is selectively etched to expose a second surface of the first die. A back side conductive layer is formed so as to contact the first surface. The second die is separated from the back side conductive layer by a first portion of the encapsulant.

Abstract: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.

Abstract: Disclosed is a light emitting device including a light emitting structure including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, a first electrode disposed on the first conductive semiconductor layer, a reflective electrode disposed on the second conductive semiconductor layer, a channel layer disposed on the light emitting structure and surrounds the reflective electrode, and a support substrate connected to the channel layer through an adhesive layer.

Abstract: A light emitting device (10) comprises a body (12) of a semiconductor material. A first junction region (14) is formed in the body between a first region (12.1) of the body of a first doping kind and a second region (12.2) of the body of a second doping kind. A second junction region (16) is formed in the body between the second region (12.2) of the body and a third region (12.3) of the body of the first doping kind. A terminal arrangement (18) is connected to the body for, in use, reverse biasing the first junction region (14) into a breakdown mode and for forward biasing at least part (16.1) of the second junction region (16), to inject carriers towards the first junction region (14). The device (10) is configured so that a first depletion region (20) associated with the reverse biased first junction region (14) punches through to a second depletion region associated with the forward biased second junction region (16).