Abstract: A system and technique are provided for providing a service address space. The system includes a service co-processor provided with a service address space. The service co-processor is attached to a main processor where the main processor is provided with a main address space. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service co-processor updates the service address space with storage delta packets received from the main processor, and the service co-processor performs diagnostic services based on command packets received from the main processor.

Abstract: An apparatus including a processor caused to: receive sizes and data block encryption data for multiple encrypted data blocks from multiple node devices, wherein data block encryption data is separately generated and used by each node device to encrypt a portion of a data set to generate one of the multiple encrypted data blocks; for each encrypted data block, generate a corresponding map entry within map data to include size and data block encryption data; and in response to receiving size and data block encryption data for all encrypted data blocks, encrypt a portion of the map data to generate an encrypted map base, wherein the portion of map data includes at least a subset of the multiple map entries, and transmit the encrypted map base to one or more storage devices to be stored within a data file along with the multiple encrypted data blocks.

Abstract: Some demonstrative embodiments include devices, systems and/or methods of controlling access to location sources. For example, a device may include a location caching controller to store cached location information in a cache based on location information retrieved from two or more location sources, to receive at least one location request from at least one application, to select between retrieving requested location information from at least one of the location sources and retrieving the requested location information from the cache, and to provide to the application a location response including the requested location information.

Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.

Abstract: An apparatus includes a processor component of a first node device caused to receive data block encryption data and an indication of size of an encrypted data block distributed to the first node device for decryption, and in response to the data set being of encrypted data: receive an indication of the quantity of sub-blocks within the encrypted data block, and a hashed identifier for each data sub-block; use the data block encryption data to decrypt the encrypted data block to regenerate data set portions from the data sub-blocks; analyze the hashed identifier of each data sub-block to determine whether all data set portions are distributed to the first node device for processing; and in response to a determination that at least one data set portion is to be distributed to a second node device for processing, transmit the at least one data set portion to the second node device.

Abstract: An apparatus may include a processor component caused to: generate map entries in map data descriptive of encrypted data blocks within a data file; use first map block encryption data to encrypt a first map extension of the map data; transmit the encrypted first map extension for storage within the data file; store the first map block encryption data within the second map extension; use second map block encryption data to encrypt a second map extension of the map data after storage of the first map block encryption data therein; transmit encrypted second map extension for storage within the data file; store the second map block encryption data within the map base; use third map block encryption data to encrypt a map base of the map data after storage of the second map block encryption data therein; and transmit the encrypted map base for storage within the data file.

Abstract: A method for creating an inconsistent backup and then a consistent backup is described. The method may include creating an inconsistent, full backup of a storage device. The method may further include creating a first snapshot of the storage device. The method may also include creating a consistent backup increment of the storage device based on the first snapshot. Additionally, the method may include adding the consistent backup increment to the inconsistent, full backup.

Abstract: The present application describes embodiments of a method and apparatus for concurrently accessing dirty bits in a cache. One embodiment of the apparatus includes a cache configurable to store a plurality of lines. The lines are grouped into a plurality of subsets the plurality of lines. This embodiment of the apparatus also includes a plurality of dirty bits associated with the plurality of lines and first circuitry configurable to concurrently access the plurality of dirty bits associated with at least one of the plurality of subsets of lines.

Abstract: A method, computer program product, and/or system for performing a selection of a plurality of auxiliary storage sites in a multi-target environment in preparation for a hyper exchange are/is provided. To perform the selection, a failure is first detected with respect to a primary storage site in the multi-target environment. Then, aggregate weights are determined based on a management policy for the plurality of auxiliary storage sites. In turn, an auxiliary storage site with a first aggregate weight is selected from the plurality of auxiliary storage sites. With the auxiliary storage site selected, the hyper exchange of a plurality of systems in a multi-target environment in response to the failure is triggered from the primary storage site to the auxiliary storage site with the first aggregate weight.

Abstract: In a multithreaded data processing system including a plurality of processor cores and a system fabric, translation entries can be invalidated without deadlock. A processing unit forwards translation invalidation request(s) received on the system fabric to a processor core via a non-blocking channel. Each of the translation invalidation requests specifies a respective target address and requests invalidation of any translation entry in the processor core that translates its respective target address. Responsive to a translation snoop machine of the processing unit snooping broadcast of a synchronization request on the system fabric of the data processing system, the translation synchronization request is presented to the processor core, and the translation snoop machine remains in an active state until a signal confirming completion of processing of the one or more translation invalidation requests and the synchronization request at the processor core is received and thereafter returns to an inactive state.

Abstract: A storage system includes a memory unit group that includes a first memory unit and a plurality of second memory units, and the first memory unit is connected to the plurality of second memory units so that data can be transmitted between the first memory unit and the second memory units. The plurality of second memory units is mounted on a same first substrate. One second memory unit of the plurality of second memory units cooperates with the first memory unit and does not cooperate with the other second memory units of the plurality of second memory units.

Abstract: According to one embodiment, a memory system includes a first storage area and a controller. The first storage area configured to store therein data sent from a host. The size of the first storage area is a first size larger than a second size. The second size is a size of a logical address space which is assigned to a memory system by the host. The controller is configured to change the second size in response to a request from the host while at least a part of data in the logical address space stays valid.

Abstract: A dual inline memory module includes a local memory and a non-volatile memory. The local memory stores data during normal operation of the dual inline memory module. The non-volatile memory includes a first portion and a second portion. The first portion stores the data located in the local memory in response to a power failure of an information handling system in communication with the dual inline memory module. The second portion stores configuration information for the dual inline memory module. The configuration information is utilized to set up the dual inline memory module in a new information handling system.

Abstract: Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.

Abstract: A multi-queue cache is configured with an initial configuration, where the initial configuration includes one or more queues for storing data items. Each of the one or more queues has an initial size. Thereafter, the multi-queue cache is operated according to a multi-queue cache replacement algorithm. During operation, access patterns for the multi-queue cache are analyzed. Based on the access patterns, an updated configuration for the multi-queue cache is determined. Thereafter, the configuration of the multi-queue cache is modified during operation. The modifying includes adjusting the size of at least one of the one or more queues according to the determined updated configuration for the multi-queue cache.

Abstract: Embodiments herein provide for avoiding address collisions in a memory device. In one embodiment, a memory controller includes a command scheduler operable to process a read-modify-write I/O command to a location in memory, to detect another I/O command to the same memory location while the read-modify-write I/O command is accessing the memory location, and to stall the other I/O command until the read-modify-write I/O command is complete while allowing a third I/O command to access the memory.

Abstract: A system, method, and computer program product is described for providing dynamic enabling and/or disabling of protection information (PI) in array systems during operation. A storage system receives a request to transition a volume from PI disabled to PI enabled during regular operation. The storage system synchronizes and purges the cache associated with the target volume. The storage system initiates an immediate availability format (IAF-PI) process to initialize PI for the associated data blocks of the volume's storage devices. The storage system continues receiving I/O requests as the IAF-PI process sweeps through the storage devices. The storage system inserts and checks PI for the write data as it is written to the storage devices. The storage system inserts PI for requested data above the IAF-PI boundary and checks PI for requested data below the IAF-PI boundary. The transition remains an online process that avoids downtime.

Abstract: A computer-implemented method for end-to-end quality of service control in distributed systems may include (1) identifying a plurality of computing systems, wherein each computing system (a) is coupled to a storage resource for the computing system, (b) hosts a plurality of applications that share the storage resource coupled to the computing system, (c) hosts a quality of service agent that limits throughput utilization of the storage resource by each of the plurality of applications, and (d) copies input/output data generated by the applications to a secondary computing system, (2) determining a throughput capacity of the secondary computing system, and (3) providing feedback to at least one quality of service agent hosted by at least one computing system to further limit throughput utilization of at least one of a plurality of applications hosted by the computing system. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A PLC data log module with backup function is proposed, the module including an internal memory configured to store the log data and to transmit the stored log data to the external memory, a backup memory configured to back-up the log data transmitted from the internal memory to the external memory and to store the backup data, and a controller configured to transmit the backup data stored in the backup memory to the external memory by controlling the backup memory when the PLC is turned off or reset.

Abstract: An apparatus comprising a processor component to: provide, to a control device, an indication of availability to perform a processing task with one or more data set portions as a node device; perform a processing task specified by the control device with the one or more data set portions; and request a pointer to a location at which to store the one or more data set portions as a data block within a data file. In response to the data set including partitioned data, for each data set portion, include a data sub-block size of the data set portion and a hashed identifier derived from a partition label of a partition in the request; receive, from the control device, the requested pointer to the location; and store each data set portion as a data sub-block within the data block starting at the location within the data file.