Abstract: Memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

Abstract: A hybrid drive and associated methods provide low-overhead storage of a hibernation file in the hybrid hard disk drive. During operation, the hybrid drive allocates a portion of solid-state memory in the drive that is large enough to accommodate a hibernation file associated with a host device of the hybrid drive. In addition to the erased memory blocks that are normally present during operation of the hybrid drive, the portion of solid-state memory allocated for accommodating the hibernation file may include over-provisioned memory blocks, blocks used to store a previous hibernation file that has been trimmed, and/or non-dirty blocks.

Abstract: Techniques are disclosed relating to per-pipeline control for an operand cache. In some embodiments, an apparatus includes a register file and multiple execution pipelines. In some embodiments, the apparatus also includes an operand cache that includes multiple entries that each include multiple portions that are each configured to store an operand for a corresponding execution pipeline. In some embodiments, the operand cache is configured, during operation of the apparatus, to store data in only a subset of the portions of an entry. In some embodiments, the apparatus is configured to store, for each entry in the operand cache, a per-entry validity value that indicates whether the entry is valid and per-portion state information that indicates whether data for each portion is valid and whether data for each portion is modified relative to data in a corresponding entry in the register file.

Abstract: An example method is provided to perform power management for a distributed storage system accessible by a cluster in a virtualized computing environment. The method may comprise, in response to detecting that a power-off requirement of a host from the cluster is satisfied, retrieving virtual machine data from a first storage resource of the host, storing the virtual machine data on a second storage resource of the host, and powering off one or more components of the host. The second storage resource is configured to be accessible when the one or more components of the host are powered off.

Abstract: A register file includes a substrate, a plurality of entries, and a plurality of read ports. Each entry includes a corresponding subset of a plurality of memory cells defined on the substrate. Each read port includes a plurality of access elements defined on the substrate. Each access element is associated with a particular common bit position of each of the entries. A plurality of entry access groups are disposed in adjacent columns on the substrate. Each entry access group is associated with a corresponding one of the plurality of entries and includes the access elements for all of the read ports for the corresponding entry.

Abstract: A storage module includes a set of memories. Each of the memories in the set of memories may be divided into a set of portions. A controller is configured to transfer data between the set of memories and a host connected through an interface. A set of channels connects the set of memories to the controller. The controller is also configured to select: a memory from the set of memories, a portion from the set of portions for the selected memory, and/or a channel from the set of channels, e.g., connected to the selected memory, based upon an identification (ID) associated with the data. The ID may be separate from the data and a write address of the data, and the selected memory, the selected portion, and the selected channel may be used to store the data.

Abstract: In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.

Abstract: In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.

Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is removed and buffered in sidecar logic. While the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request.

Abstract: A computing system includes: a memory computing block configured to: identify a partial data computing (PDC) command, a data mask, a partial data, or a combination thereof based on decoding a data packet, compute a computation result for identifying a portion of a read data to be modified according to the PDC command, the data mask, the partial data, or a combination thereof, generate a merge result based on modifying the portion of the read data according to the computation result, and a memory interface, coupled to the memory computing block, configured to transmit the merge result.

Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is removed and buffered in sidecar logic. While the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request.

Abstract: A computer-implemented method for prefetching subsequent data segments may include (1) identifying a storage system that receives sequential read requests from a sequential-access computing job and random-access read requests from a random-access computing job, (2) observing a plurality of requests to read a plurality of data segments stored by the storage system, (3) determining that the plurality of data segments are stored contiguously by the storage system and that the plurality of requests originate from the sequential-access computing job, and (4) prefetching a subsequent data segment that is directly subsequent to the plurality of data segments in response to determining that the plurality of requests originate from the sequential-access computing job. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An apparatus comprising a processor component to: receive metadata of data organization within a data set; receive indications of which node devices will be storing the data set as multiple data blocks within a data file; and receive, from each node device, a pointer request to a location within the data file for storing a data set portion as a data block. In response to the data set including partitioned data, for each request for a pointer: determine the location within the data file; generate a map data map entry for the data block; generate therein a sub-block count of data sub-blocks within the data block; generate therein a sub-entry for each data sub-block including size and a hashed identifier derived from a partition label; and provide a pointer to the node device. In response to successful storage of all data blocks, store the map data in the data file.

Abstract: A method and technique are provided for providing a service address space. The method includes providing a service co-processor with a service address space attached to a main processor. The main processor is provided with a main address space, and the service address space and the main address space include a full range of memory available to the respective service-co-processor and the main processor. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service address space is updated by receiving storage delta packets from the main processor and applying the storage delta packets to the service address space.

Abstract: A system and technique are provided for providing a service address space. The system includes a service co-processor provided with a service address space. The service co-processor is attached to a main processor wherein the main processor is provided with a main address space. The service address space and the main address space include a full range of memory available to the respective service-co-processor and the main processor. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service co-processor has a storage update receiving component for updating the service address space by receiving storage delta packets from the main processor and applying these to the service address space.

Abstract: A low semiconductor area impact mechanism for patching operations stored in a boot memory area is provided, thereby providing flexibility to such code. In this manner, current flash memory manager SCRAM, which is used for memory operations when the flash memory is unavailable can be replaced with a significantly smaller register area (e.g., a flip flop array) that provides a small patch space, variable storage, and stack. Embodiments provide such space saving without modification to the CPU core, but instead focus on the external flash memory manager. Patch code can be copied into a designated register space. Since such code used during flash memory inaccessibility is typically small, patching is provided for just a small area of the possible flash memory map, and program flow is controlled by presenting the CPU core's own address to redirect the program counter to the patch area.

Abstract: An event historian system merges stored event data snapshots into sorted event storage blocks. The system determines that a storage block contains a plurality of snapshots to be merged. A new snapshot is created into which the plurality of snapshots will be merged. The event data within the snapshots is combined and recorded into the new snapshot in a sorted order. The index files within the snapshots are combined and recorded into the new snapshot.

Abstract: Memory corruption detection technologies are described. An example processing system includes a processing core including a register to store an address of a memory corruption detection (MCD) table. The processing core can allocate a memory block of pre-determined size and can allocate a plurality of buffers within the memory block using a memory metadata word stored in an entry of the MCD table. The memory metadata word can include metadata that can identify a first bit range within the memory block for a first buffer and a second bit range within the memory block for a second buffer.

Abstract: Systems and techniques of the management of the allocation of a plurality of memory elements stored within a plurality of lockless list structures are presented. These lockless list structures (such as Slists) may be made accessible within an operating system environment of a multicore processor—and may be partitioned within the system. Memory elements may also be partitioned among these lockless list structures. When a core processor (or other processing element) makes a request for allocating a memory element to itself, the system and/or method may search among the lockless list structures for an available memory element. When a suitable and/or available memory element is found, the system may allocate the available memory element to requesting core processor. Dynamically balancing of memory elements may occur according to a suitable balancing metric, such as maintain substantial numerical equality of memory elements or avoid over-allocation of resources.

Abstract: A multi-queue cache is configured with an initial configuration, where the initial configuration includes one or more queues for storing data items. Each of the one or more queues has an initial size. Thereafter, the multi-queue cache is operated according to a multi-queue cache replacement algorithm. During operation, access patterns for the multi-queue cache are analyzed. Based on the access patterns, an updated configuration for the multi-queue cache is determined. Thereafter, the configuration of the multi-queue cache is modified during operation. The modifying includes adjusting the size of at least one of the one or more queues according to the determined updated configuration for the multi-queue cache.