Abstract: An apparatus includes processor component caused to: retrieve metadata of organization of data within a data set, and map data of organization of data blocks within a data file; receive indications of which node devices are available to perform a processing task with a data set portion; and in response to the data set including partitioned data, compare the quantities of available node devices and of the node devices last involved in storing the data set. In response to a match, for each map data map entry: retrieve a hashed identifier for a data sub-block, and a size for each of the data sub-blocks within the corresponding data block; divide the hashed identifier by the quantity of available node devices; compare the modulo value to a designation assigned to each of the available node devices; and provide a pointer to the available node device assigned the matching designation.

Abstract: A technique manages host data in a data storage array. The technique involves placing, in response to host input/output (I/O) requests from a set of host devices, host data in a container file system which is stored in a slice pool of storage slices (e.g., storage space of a standard size such as 256 MB) formed by multiple storage tiers of the data storage array. Each storage tier provides storage access at a different storage access speed. The technique further involves assigning classifications to storage slices of the slice pool which store the container file system, each classification being assigned based on storage slice access history resulting from the host I/O requests. The technique further involves relocating portions of the container file system among the multiple storage tiers according to the classifications assigned to the storage slices of the slice pool.

Abstract: Apparatus and methods of operating a memory include storing a value of an attribute of a feature vector to a pair of memory cells by programming each of the memory cells to a respective data state of three or more data states, searching for an exact match to a particular value of the attribute by applying respective voltage levels to control gates of the memory cells to activate both memory cells only when the value of the attribute is the particular value, and searching for an inexact match to the particular value of the attribute by applying respective voltage levels to control gates of the memory cells to activate both memory cells when the value of the attribute is within a range of possible values of the attribute including the particular value.

Abstract: A semiconductor device includes a plurality of memory blocks each including a plurality of memory cells, a circuit group performing a program operation, a read operation and an erase operation on a selected memory block, among the plurality of memory blocks, and a control circuit controlling the circuit group to program the memory cells of the selected memory block in a healing pattern. The healing pattern is programmed before a subsequent program operation is performed on the selected memory block. The memory cells of the healing pattern include erased memory cells and programmed memory cells arranged alternately.

Abstract: A method and system of replicating data where data is copied from a host server to a storage device in a first group of storage devices. A receipt is sent from the first group of storage devices to the host server when the data has been copied to all storage devices within the first group. The data is copied from the first group to at least one further group of storage devices. A receipt is sent from each further group of storage devices to the first group of storage devices when the data has been copied to all storage devices within each further group.

Abstract: The storage proxy method is used in a storage area network (SAN) which includes a server, a SAN device coupled to the server, and a first and a second storage systems coupled to the SAN device and their logic units mirrored with each other to form a combined mirrored logical unit. The storage proxy method includes the following steps. One of the logical units of the storage systems as a proxy logical unit is selected. The mirrored logical unit is simulated as a virtual logical unit in the SAN device, wherein the virtual logical unit has a virtual identity the same as the identity of the selected proxy logical unit. A transparent communication for management functions between the server and the proxy logical unit is provided via the virtual logical unit or a special proxy logical unit.

Abstract: To efficiently transfer of data from a cache to a memory, it is desirable that more data corresponding to the same page in the memory be loaded in a line buffer. Writing data to a memory page that is not currently loaded in a row buffer requires closing an old page and opening a new page. Both operations consume energy and clock cycles and potentially delay more critical memory read requests. Hence it is desirable to have more than one write going to the same DRAM page to amortize the cost of opening and closing DRAM pages. A desirable approach is batch write backs to the same DRAM page by retaining modified blocks in the cache until a sufficient number of modified blocks belonging to the same memory page are ready for write backs.

Abstract: A method is used in managing global caches in data storage systems. A cache entry of a global cache of a data storage system is accessed upon receiving a request to perform an I/O operation on a storage object. The cache entry is associated with the storage object. Accessing the cache entry includes holding a reference to the cache entry. A determination is made as to whether the I/O operation is associated with a sequential access. Based on the determination, releasing the reference to the cache entry is delayed.

Abstract: Two-dimensional compressed data sets can be re-aligned while preserving compression of the data. A set of one or more shifts and a corresponding set of one or more first dimension indices into a two-dimensional compressed data set for re-aligning the two-dimensional compressed data set are determined. Impact of re-aligning upon each vector in the second dimension of the two-dimensional compressed data set is determined while the two-dimensional compressed data set remains compressed. New compressed vectors are created in the second dimension resulting from re-aligning. Compression information is modified for each of the original vectors of the two-dimensional compressed data set that remain after re-aligning based, at least in part, on the new compressed vectors. A re-aligned version of the two-dimensional compressed data set is created with the new compressed vectors, and the remaining original vectors with their modified compression information.

Abstract: A method, computer program product, and computing system for defining an initial root slice for a storage system. A first data slice is defined for the storage system. The location of the first data slice of the storage system is identified within the initial root slice. A request for a supplement data slice within the storage system is received. A determination is made as to if the supplement data slice can be added within the storage system without defining a supplemental root slice for a storage system.

Abstract: A method, computer program product, and system is described that enforces a release consistency with special accesses sequentially consistent (RCsc) memory model and executes release synchronization instructions such as a StRel event without tracking an outstanding store event through a memory hierarchy, while efficiently using bandwidth resources. What is also described is the decoupling of a store event from an ordering of the store event with respect to a RCsc memory model. The description also includes a set of hierarchical read/write combining buffers that coalesce stores from different parts of the system. In addition, a pool component maintains partial order of received store events and release synchronization events to avoid content addressable memory (CAM) structures, full cache flushes, as well as direct write-throughs to memory. The approach improves the performance of both global and local synchronization events since a store event may not need to reach main memory to complete.

Abstract: Certain example embodiments provide efficient policy-based access to data stored in memory tiers, including volatile local in-process (L1) cache memory of an application and at least one managed (e.g., non-volatile) in-memory (L2) cache. Operations include receiving an access request for access to a data element in L2; detecting whether a copy of the data element is in L1; if so, copying the data element and the access policy from L2 to L1 and providing the user with access to the copy of data element from L1 if the access policy allows access to the user; and if not, determining, by referring to a copy of the access policy stored in L1, whether the user is allowed to access the data element, and, if the user is allowed to access the data element, providing the user with access to the copy of the data element from the L1 cache memory.

Abstract: A method and system are provided for providing a service address space for diagnostics collection. The method includes: providing a service co-processor attached to a main processor, wherein the service co-processor maintains an independent copy of the main processor's address space in the form of a service address space; and updating the service address space by receiving storage update packets from the main processor and applying the storage update packets to the service address space.

Abstract: A method and system are provided for providing a service address space for diagnostics collection. The system includes: a service co-processor attached to a main processor, wherein the service co-processor maintains an independent copy of the main processor's address space in the form of a service address space; and a storage update receiving component for updating the service address space by receiving storage update packets from the main processor and applying these to the service address space. An instruction pipe may be provided between the main processor and the service co-processor. The main processor may include: a service delegation component for delegating collection of diagnostic data to the co-processor by sending a collection command from the main processor to the service co-processor for collection of data from the service address space.

Abstract: Embodiments include methods, systems and computer program products for providing an extendable job structure for executing instructions on an accelerator. The method includes creating a number of data descriptor blocks, each memory location addresses and a pointer to a next of the number of the data descriptor block. The method further includes creating a last data descriptor block having memory location addresses and a last block indicator. Based on determining that additional memory is required for executing instructions on the accelerator, the method includes modifying the last data descriptor block to become a data extender block having a pointer to one of one or more new data descriptor blocks and creating a new last data descriptor block.

Abstract: A technique for managing storage device rebuild in a data storage system is disclosed. A RAID group having multiple drives with unique identifiers is provided. A drive in the RAID group that becomes inactive is identified and a timer is activated. A persistent bitmap is maintained, wherein the bitmap includes a plurality of bits and each bit indicates whether a corresponding portion of the identified drive has changed as a result of an I/O request issued while the drive is identified as inactive. If the inactive drive is subsequently identified as active before the timer expires, the timer is stopped and a rebuild procedure initiated, wherein only portions of the identified drive corresponding to bits in the bitmap are rebuilt. The bitmap is cleared and the RAID group is marked as healthy. If the timer expires before the identified drive become active, a full rebuild procedure is initiated.

Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.

Abstract: An apparatus and method for processing unit reclaiming requests in a solid state memory device. The present invention provides a method of managing a memory which includes a set of units. The method includes selecting a unit from the set of units having plurality of subunits. The method further includes determining a number of valid subunits m to be relocated from the units selected for a batch operation where m is at least 2. The selecting is carried out by a unit reclaiming process.

Abstract: A hybrid drive and associated methods provide low-overhead storage of a hibernation file in the hybrid hard disk drive. During operation, the hybrid drive allocates a portion of solid-state memory in the drive that is large enough to accommodate a hibernation file associated with a host device of the hybrid drive. In addition to the erased memory blocks that are normally present during operation of the hybrid drive, the portion of solid-state memory allocated for accommodating the hibernation file may include over-provisioned memory blocks, blocks used to store a previous hibernation file that has been trimmed, and/or non-dirty blocks.

Abstract: A system may include a command queue controller coupled to a number of clusters of cores, where each cluster includes a cache shared amongst the cores. An originating core of one of the clusters may detect a global maintenance command and send the global maintenance command to the command queue controller. The command queue controller may broadcast the global maintenance command to the clusters including the originating core's cluster. Each of the cores of the clusters may execute the global maintenance command. Each cluster may send an acknowledgement to the command queue controller upon completed execution of the global maintenance command by each core of the cluster. The command queue controller may also send, upon receiving an acknowledgement from each cluster, a final acknowledgement to the originating core's cluster.