Patents Examined by Sherman Ng
  • Patent number: 11510309
    Abstract: Provided is a display device including a display panel including a plurality of first pads, and a plurality of second pads spaced apart from the first pads, a first circuit board including first circuit pads respectively bonded to the first pads, a first driving chip electrically connected to the first circuit pads, and a first heat radiation member, and a second circuit board including second circuit pads respectively bonded to the second pads, and a second driving chip electrically connected to the second circuit pads, wherein the first heat radiation member overlaps the first driving chip and the second driving chip.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: November 22, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Wontae Kim, Jae-Han Lee
  • Patent number: 11510315
    Abstract: A multilayer substrate includes a base body including a first main surface, a first external electrode provided on the first main surface and made of metal foil, a first interlayer connection conductor, and a second interlayer connection conductor having higher conductivity than the first interlayer connection conductor. The base body includes insulating base material layers that are stacked on one another. The first interlayer connection conductor is provided at least in an insulating base material layer on which the first external electrode is provided, and is connected to the first external electrode. The second interlayer connection conductor is disposed inside the base body, and is connected to the first external electrode through the first interlayer connection conductor.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: November 22, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiromasa Koyama, Ryosuke Takada, Atsushi Kasuya
  • Patent number: 11510317
    Abstract: A circuit board may include a plurality of electrically-conductive layers separated and supported by layers of insulating material laminated together and a via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board, the via comprising a first via portion comprising electrically-conductive material and having a first diameter and a first depth from a surface of the circuit board and a second via portion comprising electrically-conductive material and having a second diameter smaller than the first diameter and a second depth from the first depth.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: November 22, 2022
    Assignee: Dell Products L.P.
    Inventors: Sandor Farkas, Bhyrav Mutnury, Steven Ethridge
  • Patent number: 11503712
    Abstract: A passive device packaging structure embedded in a glass medium according to an embodiment of the present disclosures includes a glass substrate and at least one capacitor embedded in the glass substrate. The capacitor includes an upper electrode, a dielectric layer, and a lower electrode. The glass substrate is provided on its upper surface with a cavity, the dielectric layer covers a surface of the cavity and has an area larger than that of the cavity. The upper electrode is provided on the dielectric layer. The dielectric layer and the lower electrode are connected by a metal via pillar passing through the glass substrate.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: November 15, 2022
    Assignee: Zhuhai ACCESS Semiconductor Co., Ltd
    Inventors: Xianming Chen, Yejie Hong, Benxia Huang, Lei Feng
  • Patent number: 11503718
    Abstract: Depicted embodiments are directed to an Application Specific Electronics Packaging (“ASEP”) system, which enables the manufacture of additional products using reel to reel (68a, 68b) manufacturing processes as opposed to the “batch” processes used to currently manufacture electronic products and MIDs. Through certain ASEP embodiments, it is possible to integrate connectors, sensors, LEDs, thermal management, antennas, RFID devices, microprocessors, memory, impedance control, and multi-layer functionality directly into a product.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: November 15, 2022
    Assignee: Molex, LLC
    Inventors: Marko Spiegel, Victor Zaderej, Amrit Panda
  • Patent number: 11503706
    Abstract: A stretchable circuit board includes a stretchable base material, a stretchable wiring, and a land part that is in contact with the stretchable base material. The land part is formed of a patterned metal foil, or a printed product of an electroconductive ink containing metal particles. The stretchable base material has a tensile modulus at 25° C. room temperature of 0.5 MPa to 0.5 GPa.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: November 15, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takatoshi Abe, Tomoaki Sawada, Tomohiro Fukao
  • Patent number: 11503716
    Abstract: A wiring circuit board assembly sheet is partitioned by a product region in which a plurality of wiring circuit boards serving as products are disposed in alignment and a margin region surrounding the product region with the margin region having a first area adjacent to the product region and a second area located at the opposite side of the product region with respect to the first area. The wiring circuit board assembly sheet includes a dummy wiring circuit board disposed in at least a portion of the first area and smaller than the wiring circuit board.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: November 15, 2022
    Assignee: NITTO DENKO CORPORATION
    Inventors: Takuya Taniuchi, Ryohei Kakiuchi, Naoki Shibata, Yasunari Oyabu
  • Patent number: 11500427
    Abstract: An information handling system may include a battery, a circuit board, an enclosure, and a control circuit. The circuit board may include at least one electric component, a first electrically conductive pad, and a second electrically conductive pad in proximity to the first electrically conductive pad. The enclosure may be configured to house components of the information handling system including the battery and the circuit board, and the enclosure may include a first member, a second member configured to be mechanically coupled to the first member, and a mechanical component comprising conductive material and configured to electrically short the first electrically conductive pad to the second electrically conductive pad when the first member is mechanically coupled to the second member, and cause electrical isolation of the first electrically conductive pad from the second electrically conductive pad when the first member is mechanically decoupled from the second member.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: November 15, 2022
    Assignee: Dell Products L.P.
    Inventors: Isaac Q. Wang, Anthony W. Howard
  • Patent number: 11497142
    Abstract: An assembly (110) for dissipating heat generated by a heat generating electrical component (16) which is surface mounted on a circuit board (11) in a surface mounting process. The assembly comprises a heat buffer (120) made of a thermally and electrically conducing material, and being surface mounted on the circuit board (11) so as to be soldered to a thermal flag (18) of the heat generating electrical component (16). The assembly further comprises a heat sink (12) in thermal contact with the heat buffer, and a galvanic separation (13) between the heat buffer and heat sink. The heat capacitance of the heat buffer can absorb short term increases in heat dissipation from the electrical component, before the heat is further dissipated to the galvanically separated heat sink. This may drastically improve performance of the surface mounted component.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 8, 2022
    Assignee: AROS ELECTRONICS AB
    Inventor: Jerker Hellström
  • Patent number: 11495549
    Abstract: A packaged electronic device includes a multilayer lead frame with first and second trace levels, a via level, an insulator, a conductive landing pad and a conductive crack arrest structure, the conductive landing pad has a straight profile that extends along a first direction along a side of the multilayer lead frame, the conductive crack arrest structure has a straight profile along the first direction and the conductive crack arrest structure is spaced from the conductive landing pad along an orthogonal second direction.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: November 8, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Naweed Anjum, Michael Gerald Amaro, Charles Allen Devries, Jr.
  • Patent number: 11497114
    Abstract: An inductor bridge includes a flexible substrate and a coil defined by a conductor pattern provided on or in the flexible substrate, and connects a plurality of circuit portions. The flexible substrate includes a rigid portion and a flexible portion, the rigid portion being wider than the flexible portion. The rigid portion includes the coil and a joining portion connected to another circuit. The coil includes two coil portions located at different positions in plan view, a flexible portion is located adjacent to one side of the rigid portion, and at least two coil portions of the plurality of coil portions are located on the one side when viewed from the joining portion.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: November 8, 2022
    Assignee: MURATA MANUFACTURING Co., LTD.
    Inventors: Takuya Hashimoto, Masayoshi Yamamoto
  • Patent number: 11497120
    Abstract: An electronic card includes a substrate, an electronic device bonded to the substrate via a solder bump, and configured to include a first ceiling, and a cover fixed to the substrate, provided over the electronic device, and configured to include a second ceiling that faces the first ceiling, wherein the first ceiling or the second ceiling is provided with an annular member extending in a facing direction of the first ceiling and the second ceiling, the annular member forming an annular shape along a circumferential direction of the first ceiling, wherein the first ceiling and the second ceiling form a gap between the first ceiling and the second ceiling filled with a filling material inside the annular member, and wherein the second ceiling includes a through hole at a position that overlaps the filling material when viewed in a plan view of the second ceiling.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 8, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Tsuyoshi So
  • Patent number: 11497122
    Abstract: A grid array connector system is provided that includes cables connected to pedestals that are mounted on a board. The cables include conductors that are connected to support vias positioned in openings in the board and the conductors are connected to the support vias.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: November 8, 2022
    Assignee: Molex, LLC
    Inventors: Brian Keith Lloyd, Bruce Reed, Gregory Walz, Colby Waggener, Chitaou Tsai
  • Patent number: 11490544
    Abstract: A method of fixing a flexible printed circuit (FPC) and a mobile terminal are provided. The mobile terminal includes: a rear cover; a first FPC fixedly connected to the rear cover; a front housing provided with a battery accommodation compartment; in case that a battery is installed in the battery accommodation compartment, there is a gap between the battery and the first FPC.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: November 1, 2022
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Xiaojun Yi, Shiwen Xiao
  • Patent number: 11488765
    Abstract: An electrical component, a component arrangement and a method for producing a component arrangement are disclosed. In an embodiment an electrical component includes a coil form and a winding of a wire around the coil form and a connection area comprising a wire end of the wire, wherein the connection area is configured to latch with a mounting facility.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: November 1, 2022
    Assignee: TDK ELECTRONICS AG
    Inventors: Günter Feist, Karsten Frey
  • Patent number: 11490511
    Abstract: A circuit board according to the present disclosure includes a substrate that is composed of a ceramic(s), and an electrically conductive layer that is positioned in contact with the substrate. The substrate includes a groove around the electrically conductive layer. Furthermore, an electronic device according to the present disclosure includes a circuit board with a configuration as described above, and an electronic component that is positioned on the electrically conductive layer.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 1, 2022
    Assignee: KYOCERA Corporation
    Inventor: Yuichi Abe
  • Patent number: 11488902
    Abstract: A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. A second interposer substrate is provided and includes a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method further includes joining the first interposer substrate to the second interposer substrate such that the wiring plane is provided as an interface wiring plane between the first and second bulk materials which electrically connects at least one of the first TSVs to at least one of the second TSVs.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: November 1, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Arya Bhattacherjee, H. Jim Fulford
  • Patent number: 11490503
    Abstract: A substrate with an electronic component embedded therein includes: a core structure having a cavity; a metal layer disposed on a bottom surface of the cavity of the core structure; and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate with the electronic component embedded therein has an excellent heat dissipation effect.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: November 1, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chang Hwa Park, Chi Seong Kim, Eun Heay Lee, Yo Han Song, Gun Hwi Hyung, Jae Heun Lee, Deok Man Kang, Jin Oh Park
  • Patent number: 11483927
    Abstract: A component carrier includes an electrically insulating layer structure having a first main surface and a second main surface with a through hole extending through the electrically insulating layer structure between the first main surface and the second main surface. An electrically conductive bridge structure connects opposing sidewalls of the electrically insulating layer structure delimiting the through hole. A vertical thickness of the electrically insulating layer structure is not more than 200 ?m and a narrowest vertical thickness of the bridge structure is at least 20 ?m.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: October 25, 2022
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Ismadi Bin Ismail, Valerian Yun Khim Chung, Alex Yucun Dou, Seok Kim Tay
  • Patent number: 11476569
    Abstract: An electronic device is provided. The electronic device includes an outer housing that comprises a first surface facing a first direction, a second surface facing a second direction opposite to the first direction, and a side surface surrounding a space between the first surface and the second surface, a display adapted to expose at least a portion of the display through the first surface of the outer housing, a PCB arranged between the second surface and the display in an interior of the outer housing, a communication circuit arranged on or over the PCB, a first conductive structure formed of at least one of the first surface or at least a portion of the side surface is electrically connected to the communication circuit, and a second conductive structure formed of the portion of the display electrically connected to the first conductive structure.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: October 18, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Young Kim, In Young Lee, Sang Hoon Choi, Woo Suk Kang, Jae Won Choe, Jae Bong Chun