Patents Examined by Stephanie P Duclair
  • Patent number: 11404282
    Abstract: A method of etching a film of a substrate is provided. The substrate includes an underlying region, the film and a mask. The film is provided on the underlying region. The mask is provided on the film. The method includes performing main etching on the film. The main etching is plasma etching of the film and exposes at least a part of the underlying region. The method further includes forming a protective layer on at least a side wall surface of the mask after the performing of the main etching. A material of the protective layer is different from a material of the film. The method further includes performing over-etching on the film after the forming of the protective layer. The over-etching is plasma etching of the film.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: August 2, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kosuke Ogasawara, Takahisa Iwasaki, Kentaro Ishii, Seiji Ide, Chiju Hsieh
  • Patent number: 11398386
    Abstract: In one example, a method of processing a substrate includes receiving a substrate in a processing chamber, the substrate having an etch mask positioned over an underlying layer to be etched, where the underlying layer is a silicon-containing layer. The method includes executing a first etch process that includes forming a first plasma from a first process gas that includes hydrogen bromide or chlorine and etching the underlying layer using products of the first plasma. The method includes executing a second etch process that includes forming a second plasma from a second process gas that includes fluorine and etching the substrate using products from the second plasma. The method may include alternating between the first etch process and the second etch process.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: July 26, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Yusuke Yoshida, Sergey Voronin, Shyam Sridhar, Caitlin Philippi, Christopher Talone, Alok Ranjan
  • Patent number: 11393662
    Abstract: A method of plasma processing comprises generating electrons in a source chamber, generating an electric potential gradient between the source chamber and a processing chamber by applying a first negative direct current (DC) voltage to the source chamber and a ground voltage to the processing chamber, accelerating the electrons from the source chamber through a dielectric injector and into the processing chamber using the electric potential gradient, and generating an electron-beam sustained plasma (ESP) in the processing chamber using the electrons from the source chamber.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: July 19, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Zhiying Chen, Joel Blakeney, Megan Carruth, Peter Ventzek, Alok Ranjan, Kazuya Nagaseki
  • Patent number: 11373858
    Abstract: Provided are abrasive grains, an evaluation method and a wafer manufacturing method. A predetermined amount of abrasive grains is prepared as an abrasive grain sample group, the grain diameter of individual abrasive grains in the abrasive grain sample group is measured, the number of abrasive grains in the abrasive grain sample group as a whole is counted, abrasive grains having a grain diameter equal to or smaller than a predetermined reference grain e diameter criterion which is smaller than the average grain diameter of the abrasive grain sample are defined as small grains and the number of the small grains is counted, a small grain ratio is calculated as the number ratio of the small grains occupied in the abrasive grain sample group as a whole, and a determination is made as to whether or not the small grain ratio is equal to or smaller than a predetermined threshold value.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 28, 2022
    Assignee: SUMCO CORPORATION
    Inventor: Makoto Funayama
  • Patent number: 11359121
    Abstract: A slurry containing abrasive grains and a liquid medium, in which the abrasive grains include first particles and second particles in contact with the first particles, the first particles contain cerium oxide, the second particles contain a cerium compound, and an Rsp value calculated by Formula (1) below is 1.60 or more: Rsp=(Tb/Tav)?1??(1) [in the formula, Tav represents a relaxation time (unit: ms) obtained by pulsed NMR measurement of the slurry in a case where a content of the abrasive grains is 2.0% by mass, and Tb represents a relaxation time (unit: ms) obtained by pulsed NMR measurement of a supernatant solution obtained when the slurry is subjected to centrifugal separation for 50 minutes at a centrifugal acceleration of 2.36×105 G in a case where the content of the abrasive grains is 2.0% by mass.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: June 14, 2022
    Assignee: SHOWA DENKO MATERIALS CO., LTD.
    Inventors: Tomomi Kukita, Tomohiro Iwano, Takaaki Matsumoto, Tomoyasu Hasegawa
  • Patent number: 11361959
    Abstract: A method for manufacturing a wafer product, including the steps of: chamfering a circumferential edge portion of a wafer; lapping or double-side grinding main surfaces thereof; etching; mirror-polishing the main surface; and mirror-polishing the chamfered portion. The chamfered portion has a cross-sectional shape including: a first inclined portion continuous from the first main surface; a first arc portion continuous from the first inclined portion and having a radius of curvature; a second inclined portion continuous from the second main surface; a second arc portion continuous from the second inclined portion and having a radius of curvature; and an end portion connecting the first arc portion to the second arc portion. This provides a method for manufacturing a wafer by which a variation in a chamfered cross-sectional shape in a circumferential direction caused by etching can be suppressed.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 14, 2022
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Yuya Nakatani
  • Patent number: 11355346
    Abstract: A method of processing a semiconductor wafer includes depositing a silicon layer on the semiconductor wafer. The silicon layer has a substantially uniform thickness. The silicon layer is polished to smooth the silicon layer such that the thickness is substantially uniform after polishing.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: June 7, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Guoqiang David Zhang, Mark Crooks, Tracy Michelle Ragan
  • Patent number: 11355352
    Abstract: A plasma etching method for plasma-etching an object including an etching target film and a patterned mask. The plasma etching method includes a first step of plasma-etching the etching target film using the mask, and a second step of depositing a silicon-containing film using plasma of a silicon-containing gas on at least a part of a side wall of the etching target film etched by the first step.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 7, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Keiji Kitagaito, Fumiya Kobayashi, Maju Tomura
  • Patent number: 11348798
    Abstract: A method of fabricating a semiconductor device can include providing an integrated circuit electrically coupled to a metallization pad on a semiconductor wafer, the integrated circuit and the metallization pad covered by a cap structure. A channel can be cut in a portion of the cap structure that covers the metallization pad using a cutting tool having a tip surface and a beveled side surface to expose an upper surface of the metallization pad in the channel extending in a first direction and a conductive material can be deposited in the channel to ohmically contact the upper surface of the metallization pad in the channel.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: May 31, 2022
    Assignee: Akoustis, Inc.
    Inventors: Robert C. Dry, Brook Hosse
  • Patent number: 11342192
    Abstract: A technique for making etching amounts uniform in selectively etching SiGe layers formed on a wafer with respect to at least one of an Si layer, an SiO2 layer, and an SiN layer is provided. In an etching process where SiGe layers in a wafer W in which the SiGe layers and Si layers are alternately stacked and exposed in a recess are removed by side etching, ClF3 gas and HF gas are simultaneously supplied to the wafer W. Accordingly, it is possible to make the etching rates for respective SiGe layers uniform, and it becomes possible to obtain a uniform etching amount for respective SiGe layers.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: May 24, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Nobuhiro Takahashi, Yasuo Asada, Junichiro Matsunaga
  • Patent number: 11335573
    Abstract: Disclosed is a dry etching method for etching a metal film on a substrate with an etching gas containing a ?-diketone and an additive gas, wherein the metal film contains a metal element capable of forming a complex with the ?-diketone; and wherein the amount of water contained in the etching gas is 30 mass ppm or less relative to the amount of the ?-diketone. It is preferable that the ?-diketone used for the dry etching method is supplied from a ?-diketone filled container, wherein the ?-diketone filled container has a sealed container body filled with a ?-diketone whose water content is 15 mass ppm or less relative to the ?-diketone. This etching method enables etching of the metal film while suppressing etching rate variations from the initial stage to the later stage of use of the filled container.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: May 17, 2022
    Assignee: Cental Glass Company, Limited
    Inventors: Kunihiro Yamauchi, Takashi Masuda, Akifumi Yao
  • Patent number: 11328909
    Abstract: Exemplary methods for conditioning a processing region of a semiconductor processing chamber may include forming conditioning plasma effluents of an oxygen-containing precursor in a semiconductor processing chamber. The methods may include contacting interior surfaces of the semiconductor processing chamber bordering a substrate processing region with the conditioning plasma effluents. The methods may also include treating the interior surfaces of the semiconductor processing chamber.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 10, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Hanshen Zhang, Zhenjiang Cui, Nitin Ingle
  • Patent number: 11312882
    Abstract: A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (H2O2), ammonium persulfate ((NH4)2S2O8), peroxymonosulfuric acid (H2SO5), ozone (O3) in de-ionized water, and sulfuric acid (H2SO4).
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Yin Lin, Wen-Kuei Liu, Teng-Chun Tsai, Shen-Nan Lee, Kuo-Cheng Lien, Chang-Sheng Lin, Yu-Wei Chou
  • Patent number: 11315801
    Abstract: Methods for processing a workpiece are provided. The workpiece can include a ruthenium layer and a copper layer. In one example implementation, a method for processing a workpiece can include supporting a workpiece on a workpiece support. The method can include performing an ozone etch process on the workpiece to at least a portion of the ruthenium layer. The method can also include performing a hydrogen radical treatment process on a workpiece to remove at least a portion of an oxide layer on the copper layer.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: April 26, 2022
    Assignees: BEIJING E-TOWN SEMICONDUCTOR TECHNOLOGY CO., LTD, MATTSON TECHNOLOGY, INC.
    Inventors: Qi Zhang, Haichun Yang, Hua Chung, Michael X. Yang
  • Patent number: 11302533
    Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: April 12, 2022
    Assignee: Tessera, Inc.
    Inventors: John Christopher Arnold, Sean D. Burns, Yann Alain Marcel Mignot, Yongan Xu
  • Patent number: 11289339
    Abstract: A plasma processing method executed by a plasma processing apparatus includes a first step, a second step, and an etching step. In the first step, the plasma processing apparatus forms a first film on a processing target in which a plurality of openings having a predetermined pattern are formed. In the second step, the plasma processing apparatus forms a second film having an etching rate lower than that of the first film on the processing target on which the first film is formed, and having different film thicknesses on the side surfaces of the openings according to the sizes of the openings. In the etching step, the plasma processing apparatus performs etching from above the second film under a predetermined processing condition until a portion of the first film is removed from at least a portion of the processing target.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: March 29, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Masahiro Tabata
  • Patent number: 11289338
    Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
  • Patent number: 11279852
    Abstract: Described herein are chemical mechanical polishing (CMP) slurry compositions, such as CMP slurry compositions for polishing an indium tin oxide (ITO) layer, along with methods of fabricating a semiconductor device using such a CMP slurry composition. The CMP slurry composition can include a polishing particle, a dispersing agent, an auxiliary oxidizing agent, and a sugar alcohol compound.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: March 22, 2022
    Inventors: Eunsung Seo, Chang Gil Kwon, Sung Pyo Lee, Dongchan Kim, Bo Yun Kim, Jun Ha Hwang
  • Patent number: 11254870
    Abstract: According to one embodiment, an etching solution is provided. The etching solution is used for etching of silicon nitride. The etching solution includes: phosphoric acid; tetrafluoroboric acid; a silicon compound; water; and at least one of sulfuric acid and an ionic liquid.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: February 22, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaaki Hirakawa, Ikuo Uematsu, Takahiro Kanai
  • Patent number: 11257682
    Abstract: A method of etching an organic or hybrid inorganic/organic material. The method etches molecular layer deposition coatings. An etching cycle comprises a first half reaction exposing the coating to a precursor. A second half reaction exposes a second precursor, removing or etching a portion of the coating.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: February 22, 2022
    Assignee: UChicago Argonne, LLC
    Inventors: Matthias John Young, Steven Payonk Letourneau, Devika Choudhury, Jeffrey W. Elam, Angel Yanguas-Gil, Anil U. Mane