Abstract: A method of obtaining a Viterbi decoded value is disclosed. A decision output is stored to one of a plurality of buffer elements, wherein at least one other buffer element in the plurality is not changing; and data is exposed in the buffer element. A plurality of stored decision outputs is obtained from the plurality of buffers elements. The obtained plurality of stored decision outputs is processed to obtain a Viterbi decoded value.

Abstract: An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic, a non-delayed signal-capture element, a delayed signal-capture element and a comparator. The non-delayed signal-capture element captures an output from the processing logic at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element also captures a value from the processing logic. An error detection circuit and error correction circuit detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator. The comparator compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: A soft error recoverable storage element suitable for use in latches, flip-flops, static ram memory cells and microprocessor pipeline stages. The storage element employs a redundant copy of the stored data value and a feedback loop. One embodiment employs an interlocking four inverter loop with gating devices that blocks the propagation of a soft error induced change of state and causes the storage element to recover its original stored data state.

Abstract: A method is used that substantially simultaneously trellis encodes data to be modulated onto multiple tones. The embodiments of the present invention comprise the steps of: (a) using a first input operand comprising state bits for a first trellis stage; (b) using a second input operand comprising a plurality of input data bits; and (c) generating an output comprising output data bits and output state bits from a first or later trellis stage.

Abstract: This is disclosed a communication apparatus. A receiving unit receives plural data frames which are transmitted from other communication apparatus. An error detection unit checks whether each data frame is received correctly or incorrectly. A determination unit estimates a first overhead and a second overhead and determines whether or not to send a block acknowledgement frame by comparing the first and the second overheads. The determination unit estimates the first overhead being caused by sending the block acknowledgement frame and the second overhead being caused by not sending the block acknowledgement frame. The receiving unit receives the data frames which are retransmitted from the other communication apparatus after a certain period of time has passed without sending the block acknowledgement frame, the data frames retransmitted from the other communication apparatus including both data frames which are correctly received and incorrectly received.

Abstract: Disclosed is a communication system that transmits data through a transmission path between a transmission side apparatus and a reception side apparatus, wherein the transmission side apparatus comprises a coding apparatus that creates redundantly-coded data from original data; a transmitting apparatus that sends the coded data coded by the coding unit to the transmission path; and a coding rate determining apparatus that sets and controls a coding rate in the coding unit, wherein the reception side apparatus comprises a receiving apparatus that receives the coded data sent through the transmission path; a decoding apparatus that decodes the original data from the coded data received; and a loss rate estimating apparatus that measures the loss rate on the path of the coded data sent, and wherein the coding rate determining apparatus of the transmission side apparatus varies and controls the coding rate in the coding apparatus based on the loss rate obtained.

Abstract: Methods and techniques are disclosed for correcting the effect of cycle slips in a coherent communications system. A signal comprising SYNC bursts having a predetermined periodicity and a plurality of known symbols at predetermined locations between successive SYNC bursts is received. The received signal is partitioned into data blocks. Each data block encompasses at least data symbols and a set of check symbols corresponding to the plurality of known symbols at predetermined locations between a respective pair of successive SYNC bursts in the signal. Each data block is processed to detect a cycle slip. When a cycle slip is detected, the set of check symbols of the data block are examined to identify a first slipped check symbol, and a phase correction applied to data symbols of the data block lying between the first slipped check symbol and an end of the data block.

Abstract: A receiver is provided, which is adapted to receive MPE-FEC frames and to correct erroneous sections within a received MPE-FEC frame by detecting unreliable sections and storing in an erasure list (“ESL”) table compressed data that includes the base address of each detected erroneous section, together with the respective section's size. The size of the ESL table may be fixed, or it may correlate, or dynamically change according to the actual number of detected erroneous sections. The data stored in the erasure list may then be forwarded to a decoder to correct erroneous sections. The erroneous sections may be detected by using CRC, and the decoder may be a Reed-Solomon decoder.

Abstract: A method of satisfying a specified run length constraint is disclosed. A systematically error correction encoded sequence of received symbols is received, wherein the received symbols include data symbols and parity symbols. The parity symbols are interleaved with the data symbols to produce interleaved symbols that satisfy the specified run length constraint.

Abstract: A method and system for command queuing in disk drives may improve performance by queuing multiple commands and sequentially executing them automatically without firmware intervention. The method may use a number of queues, e.g., a staging queue for commands to be executed, an execution queue for commands currently being executed, and a holding queue for commands which have been executed but have not received a status report from a host. With the pipelined nature of queued commands, when data requested by one command are being sent to the host, the queue logic may already be fetching data for the next command. If an error occurs in the transmission, commands in the queues may backtrack and restart from the point where data were last known to have been successfully sent to the host.

Abstract: Systems and methods are disclosed herein for improving the sensitivity of satellite data decode in a satellite navigation receiver. The low signal ephemeris data decoding system of the present disclosure achieves a 5 db improvement in decoding sensitivity over conventional system by operating down to a CN0 of 21 dB-Hz. The improved sensitivity is achieved through a combination of reducing the number of data bits to be decoded, overcoming the inherent differential decoding problem of an all data bit polarity inversion, improving the probability of seeing single bit decoding error in an ephemeris word, running the parity correction algorithm, and reducing the undetected word error rate. The improved sensitivity makes it possible to predict the orbit of the satellite and to determine the receiver's location with higher accuracy even when operating in challenging signal conditions.

Abstract: Operational parameter adaptable LDPC (Low Density Parity Check) decoder. A novel means is presented by which LDPC coded signal can be decoded, and any one or more operational parameters can be adjusted during the decoding processing. For example, the original information extracted from a received LDPC coded signal (e.g., log likelihood ratios (LLRs)), can be modified during (or before) the iterative decoding processing performed in accordance with decoding an LDPC coded signal. Such modification of an operational parameter can include any one or combination of scaling, compression (and expansion/decompression), adding an offset to or subtracting an offset from, scaling, rounding, and/or some other modification of an operational parameter. The bit (or variable) edge messages and/or the check edge messages can also undergo modification during decoding processing.

Abstract: Buffering packets of a media stream for transmission from a transmitting device to a receiving device. Media packets are formed from at least one kind of media information in a stream generator; forward error correction data is formed on the basis of the media packets; one or more repair packets are formed on the basis of the forward error correction data; and a transmission schedule is generated for packets to be transmitted. In addition, hypothetical decoding is also performed according to the transmission schedule. The hypothetical decoding comprises buffering the packets to be transmitted according to the transmission schedule to a hypothetical decoding buffer; and controlling the buffer occupancy level of the hypothetical decoding buffer by controlling the operation of the stream generator.

Abstract: Computer communications that are to be recorded are visible to a network interface on a recording computer. The network interface receives the packets to be recorded. The network layer of the recording computer implements a subset of the normal IP module in the network layer. The IP module in the network layer assumes that most IP datagrams are correctly addressed, internally consistent and of the expected protocol type. The recording computer allocates the received datagrams to a recording session based upon at least a first value of a field that is at a fixed position within the datagram. The datagrams for a session are ordered into an ordered recording stream based upon a timestamp within the datagram. The datagrams are also checked for criteria that indicate an error condition. The allocated and ordered datagrams are recorded or associated with other datagrams that have been allocated to the same session.

Abstract: A communication apparatus includes a storage unit, a row processing unit, and a column processing unit. The row processing unit repeatedly performs row processing to calculate a column-processing LLR for each column and each row in a check matrix. The column processing unit calculates a row-processing LLR for each column and each row of the check matrix, and repeatedly performs column processing to store in the storage unit the minimum value k of absolute values of the row-processing LLR. The row processing unit and the column processing unit alternately performs their processing. The row processing unit performs calculation using an approximate minimum value while the column processing unit cyclically updates the minimum k value of each row.

Abstract: Example embodiments provide a method and apparatus of correcting error data due to charge loss within a non-volatile memory device including a plurality of memory cells. The method of correcting error data within the non-volatile memory devices may include detecting error data in a second data group by comparing a first data group read from memory cells in response to a first voltage with the second data group read from memory cells in response to a second voltage. The second voltage is higher than the first voltage. Error data in the first data group is detected by error-correcting code (ECC). Re-writing data in the memory cells is performed by correcting error data in the first data group and error data in the second data group. A central processing unit (CPU) may detect error in the second data group. The second data group may be read through a page buffer and compared with the first data group stored in a SRAM. The detected error may be updated to the page buffer.

Abstract: The present invention relates to a decoding method and system for stochastic decoding of LDPC codes. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital bits. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the LDPC code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information bits. If an equality node is in a hold state a chosen bit is provided from a corresponding edge memory which is updated by storing output bits from the equality node when the same is in a state other than a hold state.

Abstract: A method includes checking a first parameter that indicates whether parity generation and checking for a at least a sub-portion of a cache line is disabled, setting at least one parity bit, corresponding to the sub-portion, in the cache line with a second parameter that indicates an action to perform when the first parameter indicates that parity generation and checking is disabled, passing the at least one set parity bit with the sub-portion to a processor for processing, and performing the action when the sub-portion is processed by the processor, wherein the processor performs the action.

Abstract: An error correction circuit and method for reducing a miscorrection probability and a semiconductor memory device including the circuit are provided. The error correction circuit includes an error check and correction (ECC) encoder and an ECC decoder. The ECC encoder generates syndrome data enabling h-bit error correction based on information data and a generator polynomial, where “h” is 2 or an integer greater than 2. The ECC decoder may operate in a single mode for detecting an error position with respect to a maximum of (h?j) bits in the information data based on encoded data including the information and the syndrome data, where “j” is 1 or an integer greater than 1.