Abstract: A position detection error correcting method that corrects position detection errors using a limited storage capacity, by calculating position detection error correction values by four simple arithmetic operations at startup to reduce a startup time delay and consumption of a storage capacity even when a portion containing steep error variations exists. Detection error correction values of a position detector are expressed by a correction function using a periodic function, and correction parameters of the correction values are stored in advance in a non-volatile memory. At startup, these correction parameters are read out, and a position detection error correction value corresponding to each detected position is calculated and stored in a random access memory. The output position detection error correction value detector corresponding to each detected position is read out from the random access memory and a corrected detected position value corrected for the detected position value error is calculated.

Abstract: Methods and apparatus for designing spherical lattice codebooks for use in data transmission systems are provided. A spherical lattice codebook is constructed by determining the channel statistics of one or more channels, which can be accomplished by observing a sufficiently large set of channel realizations. After determining the channel statistics, an expression for the error probability of the decoder or expressions for bounds on the error probability and expressions for the corresponding gradients are determined. The gradient is then used in an optimization technique to produce a spherical lattice codebook which is subsequently used for transmission.

Abstract: Symbol by symbol MAP detection for signals corrupted by colored and/or signal dependent noise. A novel means is presented for recursive calculation of forward metrics (?), backward metrics (?), and corresponding soft information (e.g., which can be provided as LLRs (log likelihood ratios)) within communication systems in which a trellis can be employed to perform demodulation of a received signal sequence. For signals that have been corrupted by colored and/or signal dependent noise, this means provides for the ability to perform novel soft information calculation for subsequent use in iterative decoding processing. Many types of communication channels can benefit from this novel means of detection including communication channels within hard disk drives (HDDs).

Abstract: An interface system is provided between a source component (210) and a destination component (220) having multiple parallel lines for transmitting data or parity bits (231-234, 251-253) and one or more spare lines (241-243). An error detection means (222) identifies one or more faulty lines. A mapping means (228) re-routes data or parity from a faulty line to a spare line. A communication link (208) is provided for communicating the re-routing between the source component (210) and the destination component (220). The error detection and mapping can be repeated to detect and re-route sequential multiple-bit line errors using additional spare lines (241-243).

Abstract: An apparatus and method are disclosed for correcting errors in data obtained from read operations on a storage medium. Errors that occur in a minority of read operations for the data are corrected by a voting technique. The data may then be processed with error correcting code to correct errors that occur in a majority of read operations.

Abstract: Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords. Fixed spacing is employed to intersperse parity bits among information bits when generating a codeword. According to this fixed spacing, a same number of information bits is placed between each of the parity bits within the codeword. If desired, the order of the parity bits may be changed before they are placed into the codeword. Moreover, the order of the information bits may also be modified before they are placed into the codeword. The FEC encoding employed to generate the parity bits from the information bits can be any of a variety of codes include Reed-Solomon (RS) code, LDPC (Low Density Parity Check) code, turbo code, turbo trellis coded modulation (TTCM), or some other code providing FEC capabilities.

Abstract: A memory system includes code data generating section which generates code data based on write data. A nonvolatile semiconductor memory stores the write data and the code data for the write data and outputs read data and the code data for the read data. An error correcting section is configured to correct an error bit included in the read data using the read data and the code data for the read data, and outputs the read data which includes the error bit in accordance with a setting. An interface section receives the write data from outside of the memory system, and outputs the read data to outside of the memory system.

Abstract: A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.

Abstract: A control device managing a plurality of nodes transmitting and receiving data containing an error correcting code, comprises means accepting, when any one of the nodes detects an uncorrectable error from the data containing the error correcting code, a signal transmitted by the node detecting the error, means judging from a record of the detection of a first node, when accepting the signal from a second node receiving data transmitted by the first node, whether or not the first node has detected the uncorrectable error from the data transmitted to the second node, and means stopping, when the first node has detected the uncorrectable error from the data transmitted to the second node, a process attributed to the acceptance of the signal from the second node.

Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.

Abstract: A system for generating CRC code words associated with data ranging up to w-bytes in width to be communicated over a communications channel includes a first plurality of serially coupled code-generation blocks each for generating a CRC value based on data input to each block, respective blocks of the first plurality configured for receiving data inputs having respective byte widths ranging from 2N+M to 2N?L+M, where N is equal to log2(w), and M is an offset value, and L is a whole number based on a maximum propagation delay criteria; a second plurality of parallel coupled code-generation blocks each for generating a CRC value based on data inputs, respective blocks of the second plurality configured for receiving data having respective byte widths ranging from 2N?L?1+M to 20; and, a device for selecting particular CRC code generation blocks in the first and second pluralities to be included in a CRC calculation based on the data input; wherein any number of data input bytes may be processed.

Abstract: Systems and methods are provided for correcting absorb sets and near absorb sets in the (2048, 1723) LDPC code used in 10GBase-T transmission systems. Absorb sets and near absorb sets correspond to error patterns that, due to the structure and imperfections of the LDPC code, cannot easily be corrected using standard correction methods. To correct these error patterns, a set of failed syndrome checks associated with the error pattern can be identified, and the 4, 8, 12, or 16 error patterns associated with the failed syndrome checks can be determined. The codeword may then be corrected based on the error pattern that most likely occurred.

Abstract: According to a method and apparatus taught herein, a decoding circuit and method decode linear block codes based on determining joint probabilities for one or more related subsets of bits in received data blocks. The use of joint probabilities enables faster and more reliable determination of received bits, meaning that, for example, joint probability decoding requires fewer decoding iterations than a comparable decoding process based on single-bit probabilities. As a non-limiting example, the decoding circuit and method taught herein provide advantageous operation with Low Density Parity Check (LDPC) codes, and can be incorporated in a variety of communication systems and devices, such as those associated with wireless communication networks.

Abstract: Protection of access information in wireless communications is achieved by transmitting access information related to configuration to a terminal, receiving a result of a countermeasure procedure performed by the terminal, deciding whether the configuration is correct or not based on the received result, and if not correct, allowing the terminal to receive access information, or if correct, performing the configuration.

Abstract: Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However, by employing error correction coding (ECC), embodiments of the present invention may detect and correct these potential errors that may occur in the power-saving mode. Furthermore, a partial ECC check cycle is employed to check and correct a sub-set of the memory cells during a periodic self-refresh process that occurs during the power-saving mode.

Abstract: A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.

Abstract: Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.

Abstract: Wireless transmission of data is effected across a communications channel defined by a communications medium by means of an encoder, operable to apply a low density parity check (LDPC) code to data for transmission. The LDPC code is irregular with respect to the degree of variable nodes, and so the transmitter further comprises means for sorting encoded data with respect to the corresponding variable node degree, and modulation and distribution means for allocating encoded and sorted data onto the communications medium. The distribution of the data onto the communications medium is carried out with respect to a prior established pre-coding algorithm, such as SVD.