Abstract: A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.

Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.

Abstract: An electronic device and the manufacturing method thereof are provided. The electronic device includes a semiconductor die, a conductive structure electrically coupled to the semiconductor die, an insulating encapsulant encapsulating the semiconductor die and the conductive structure, and a redistribution structure disposed on the insulating encapsulant and the semiconductor die. The conductive structure includes a first conductor, a second conductor, and a diffusion barrier layer between the first conductor and the second conductor. The redistribution structure is electrically connected to the semiconductor die and the first conductor of the conductive structure.

Abstract: An image sensor including a light source configured to emit an optical signal to a target object, and a pixel array including a first pixel configured to generate pixel signals based on the optical signal reflected from the target object, the first pixel including a first photo gate group having at least two photo gates that are configured to receive first gate signals with a first phase difference from the optical signal in a time interval and a second photo gate group having at least two photo gates configured to receive second gate signals with a second phase difference from the optical signal in the time interval, may be provided.

Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.

Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory comprises a plurality of memory stacks neighboring each other in a first direction and a second direction, the second direction intersecting the first direction, a plurality of first liner layers covering sidewalls of memory stacks that neighbor each other in the second direction, the plurality of first liner layers extending in the second direction, a plurality of first air gaps located in spaces covered by the first liner layers, and a plurality of second air gaps located between each pair of memory stacks that neighbor each other in the first direction, the plurality of second air gaps extending in the second direction.

Abstract: A semiconductor device includes an n-type drift layer formed on a semiconductor substrate having an off-angle, plurality of p-type pillar regions formed in the drift layer, and a surface electrode formed on the drift layer including the plurality of p-type pillar regions. A plurality of withstand voltage holding structures which are p-type semiconductor regions are formed in a surface layer of the drift layer including the plurality of p-type pillar regions to surround an active region. Each of the plurality of p-type pillar regions has a linear shape extending in a direction of the off-angle of the semiconductor substrate. Each of the plurality of withstand voltage holding structures has a frame-like shape including sides extending in parallel with the plurality of p-type pillar regions and sides perpendicular to the plurality of p-type pillar regions in a planar view.

Abstract: An image sensor includes a photodiode within a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL), a plurality of dielectric layers over the CESL and a plurality of metallization layers in the plurality of dielectric layers. At least one dielectric layer of the plurality of dielectric layers includes a low-k dielectric material. An opening is extended through the plurality of dielectric layers to expose a portion of the CESL above an active region of the photodiode. A cap layer is on sidewalls of the opening. The cap layer includes a dielectric material having a higher moisture resistance than the low-k dielectric material.

Abstract: A semiconductor device includes a composite pn-junction structure in a semiconductor substrate, wherein the composite pn-junction structure has a first junction grading coefficient m1, with m1?0.50. The composite pn-junction structure includes a first partial pn-junction structure and a second partial pn-junction structure, wherein the first partial pn-junction structure has a first partial junction grading coefficient m11, and wherein the second partial pn-junction structure has a second partial junction grading coefficient m12. The first partial junction grading coefficient m11 is different to the second partial junction grading coefficient m12, with m11?m12. At least one of the first and second partial junction grading coefficients m11, m12 is greater than 0.50, with m11 and/or m12>0.50. The first junction grading coefficient m1 of the composite pn-junction structure is based on a combination of the first and second partial junction grading coefficients m11, m12.

Abstract: Disclosed is a display panel, including a display device board and an encapsulation layer; the display device board includes a display area and a peripheral area; the encapsulation layer includes a first organic layer, a first inorganic layer, a second organic layer and a second inorganic layer, and the first organic layer includes at least two annular members, and the annular member includes four strip members, and the strip member covers at least a portion of a pixel unit of the display device board, and the first inorganic layer, the second organic layer and the second inorganic layer are sequentially stacked.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: A foil structure with generation of visible light via LED technology has a carrier foil and an LED chip for generation of UV light. The LED chip is disposed on a first portion of the carrier foil and is provided with a light output face for emission of the UV light. The foil structure further has a color reaction layer for conversion of the UV light into the visible light, wherein the color reaction layer is disposed on a second portion of the carrier foil. The carrier foil is folded over in such a way that the second portion of the carrier foil is disposed above the first portion of the carrier foil and the color reaction layer is disposed above the LED chip or in a manner laterally offset relative to the LED chip.

Abstract: Methods for hybrid bonding include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. The conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

Abstract: An organic light emitting diode (OLED) display device includes a flexible substrate, a thin-film transistor (TFT) layer, an OLED light emitting layer, a barrier layer, and an encapsulation layer. The encapsulation layer covers the barrier layer, and a portion of the encapsulation layer located at an outside of the barrier layer includes a first inorganic layer and a second inorganic layer. A protection layer is disposed on a portion of the first inorganic layer over surface the barrier layer, and the protection layer completely covers the barrier layer.

Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips with interconnect structures are disclosed. LED chips are provided that include first interconnects electrically coupled to an n-type layer and second interconnects electrically connected to a p-type layer. Configurations of the first and second interconnects are provided that may improve current spreading by reducing localized areas of current crowding within LED chips. Various configurations are disclosed that include collectively formed symmetric patterns of the first and second interconnects, diameters of certain ones of either the first or second interconnects that vary based on their relative positions in LED chips, and spacings of the second interconnects that vary based on their distances from the first interconnects. In this regard, LED chips are disclosed with improved current spreading as well as higher lumen outputs and efficiencies.

Abstract: A microelectromechanical systems package structure includes a first substrate, a transducer unit, a semiconductor chip and a second substrate. The first substrate defines a through hole. The transducer unit is electrically connected to the first substrate, and includes a base and a membrane. The membrane is located between the through hole and the base. The semiconductor chip is electrically connected to the first substrate and the transducer unit. The second substrate is attached to the first substrate and defines a cavity. The transducer unit and the chip are disposed in the cavity, and the second substrate is electrically connected to the transducer unit and the semiconductor chip through the first substrate.

Abstract: In an embodiment, a process for making a thermal interface article comprises shaping a flowable composite comprising a flowable matrix composition, a plurality of magnetic, thermally conductive particles having an average length greater than a thickness or diameter, wherein the plurality of magnetic, thermally conductive particles have magnetic or superparamagnetic nanoparticles attached thereto, to provide the flowable composite in a shape comprising a first surface and an opposing second surface, and having a Z-axis perpendicular to the first surface and the opposing second surface; subjecting the flowable composite to a rotating magnetic field and to a vibrational force in an amount and for a time effective to align the average length of the plurality of magnetic, thermally conductive particles along the Z-axis; and solidifying the flowable matrix composition to provide the thermal interface, wherein the thermal interface has a Z-direction thermal conductivity of at least 1.0 W/mK.

Abstract: The invention relates to an electrooptical device comprising a semiconductor substrate having a front side and a back side, at least one photonic component arranged on the front side of the semiconductor substrate, the photonic component comprising an active layer made of a non-linear optical material, wherein at least one cavity, extends through the semiconductor substrate and connects the active layer on the front side of the semiconductor substrate with the back side of the semiconductor substrate.

Abstract: An optoelectronic semiconductor component includes a semiconductor layer sequence that generates radiation, the semiconductor layer sequence has an emission side and a rear side opposite said emission side, a mirror for the generated radiation on the rear side, a carrier that is transmissive to the radiation generated, on the emission side, and a reflector housing on side surfaces of the carrier, the reflector housing is impermeable to the generated radiation and configured for diffuse reflection of generated radiation and includes a radiation exit opening, wherein at least one of a width of an opening in the reflector housing and an area of the radiation exit opening decrease(s) in a direction away from the emission side, and a maximum emission of the generated radiation takes place in an emission angle range of 30° to 60°, relative to a perpendicular to the emission side.

Abstract: A lens module includes a circuit board, a photosensitive chip, a mounting bracket, a filter, a lens base, and a lens. The circuit board defines a first through hole. The photosensitive chip is mounted within the first through hole. Gold fingers are mounted on the circuit board surrounding the photosensitive chip. Metal wires are mounted on a periphery of the photosensitive chip. Each of the metal wires is coupled to a corresponding one of the gold fingers. The metal wires are encapsulated by a colloid so that the metal wires do not contact each other. The mounting bracket is mounted on the circuit board. The filter is mounted on the mounting bracket and aligned with the photosensitive chip. The lens base is mounted on the mounting bracket. The lens is mounted within the lens base and aligned with the photosensitive chip.