Abstract: The present disclosure relates to a solid-state imaging element, a sensor apparatus, and an electronic device capable of achieving better characteristics. A transistor constituting a pixel includes: a gate electrode having at least two fin portions formed so as to be buried from a planar portion planarly formed on a surface of a semiconductor substrate toward an inside of the semiconductor substrate; and a channel portion provided across a source and a drain so as to be in contact with side surfaces of the fin portions via an insulating film. In addition, a width of the channel portion is formed to be narrower than a depth of the fin portion. The present technology is applicable to a CMOS image sensor, for example.

Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure present on a channel region portion of the plurality of suspended nanowires. The gate structure has a uniform length extending from an upper surface of the gate structure to the base of the gate structure. The semiconductor device further includes a dielectric spacer having a uniform composition in direct contact with the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.

Abstract: A multiple-atom silicon quantum dot is provided that includes multiple dangling bonds on an otherwise H-terminated silicon surface, each dangling bonds having one of three ionization states of +1, 0 or ?1 and corresponding respectively to 0, 1, or 2 electrons in a dangling bond state. The dangling bonds together in close proximity and having the dangling bond states energetically in the silicon band gap with selective control of the ionization state of one of the dangling bonds. A new class of electronics elements is provided through the inclusion of at least one input and at least one output to the multiple dangling bonds. Selective modification or creation of a dangling bond is also detailed.

Abstract: A semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. A side surface of the first adhesive layer is recessed from side surfaces of the first and second semiconductor chips.

Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.

Abstract: A memristor may include an exchange-coupled composite (ECC) portion to provide three or more nonvolatile magneto-resistive states. The ECC portion may include a continuous layer and a granular layer magnetically exchange coupled to the continuous layer. A plurality of memristors may be used in a system to, for example, define a neural network.

Abstract: Light emitting diodes, components, and related methods, with improved performance over existing light emitting diodes. In some embodiments, light emitter devices included herein include a submount, a light emitter, a light affecting material, and a wavelength conversion component. Wavelength conversion components provided herein include a transparent substrate having an upper surface and a lower surface, and a phosphor compound disposed on the upper surface or lower surface, wherein the wavelength conversion component is configured to alter a wavelength of a light emitted from a light source when positioned proximate to the light source.

Abstract: According to one embodiment, a display device includes a first common electrode, a second common electrode separated from the first common electrode in a first direction and a first metal wiring extending in the first direction and overlapping the first common electrode and the second common electrode. The first metal wiring is located between the first common electrode and the second common electrode, and the first metal wiring includes a first end portion overlapping one of the first common electrode and the second common electrode.

Abstract: The present disclosure provides a projection device for a 3D printer, the projection device including a light source and a display panel for displaying an image to be printed, the image to be printed including a light transmission region and/or a light shielding region. The projection device is configured such that lights emitted from the light source pass through the light transmission region, and that the lights passing through the light transmission region from the light source are non-polarized lights. The present disclosure also provides a 3D printer.

Abstract: The present disclosure relates to reducing the size of a solid-state imaging apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, comprising a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned, and a second structure body, comprising an output circuit unit for outputting a pixel signal. The output circuit unit, including a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.

Abstract: A layout of a semiconductor device is stored on a non-transitory computer-readable medium. The layout includes a first transistor in an active device region and a second transistor in a guard ring region. The first transistor includes a first channel region, a first gate structure across the first channel region, and a first source region and a first drain region on opposite sides of the first channel region. The second transistor includes a second channel region, a second gate structure across the second channel region, a second source region and a second drain region on opposite sides of the second channel region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.

Abstract: A photodiode that multiplies a charge generated by photoelectric conversion in an avalanche region includes: a p? type semiconductor layer having interfaces; an n+ type semiconductor region located inside the p? type semiconductor layer and in contact with the interface; an n+ type semiconductor region located inside the p? type semiconductor layer and connected to the n+ type semiconductor region; and a p type semiconductor region located between the n+ type semiconductor region and the interface, wherein the n+ type semiconductor region, the n+ type semiconductor region, and the p type semiconductor region each have a higher impurity concentration than the p? type semiconductor layer, the avalanche region is a region between the n+ type semiconductor region and the p type semiconductor region inside the p? type semiconductor layer, and the n+ type semiconductor region has a smaller area than the n+ type semiconductor region in planar view.

Abstract: The present invention relates to providing a thin film transistor substrate containing a protective film, which can impart high driving stability. The thin film transistor substrate contains a thin film transistor and a protective film containing a cured product of a siloxane composition which covers the thin film transistor, wherein the thin film transistor has a semiconductor layer made of an oxide semiconductor, and wherein the siloxane composition contains polysiloxane, a fluorine-containing compound, and a solvent.

Abstract: This disclosure is directed to two-dimensional conformal optically-fed phased arrays and methods for manufacturing the same. The method includes providing a wafer substrate, depositing a first cladding layer on the wafer substrate, and depositing a core layer on the first cladding layer. The method further includes photolithographically patterning the core layer to provide a plurality of optical waveguide cores, and depositing a second cladding layer on the core layer to cover the plurality of optical waveguide cores to provide a plurality of optical waveguides. In addition, the method includes forming a plurality of antennas on the second cladding layer, each antenna of the plurality of antennas located near a termination of a corresponding optical waveguide of the plurality of optical waveguides, and providing a plurality of photodiodes on the second cladding layer, each photodiode of the plurality of photodiodes connected to a corresponding antenna.

Abstract: A semiconductor device includes a semiconductor body and an insulated gate contact on a surface of the semiconductor body over an active channel in the semiconductor device. The insulated gate contact includes a channel mobility enhancement layer on the surface of the semiconductor body, a diffusion barrier layer over the channel mobility enhancement layer, and a dielectric layer over the diffusion barrier layer. By using the channel mobility enhancement layer in the insulated gate contact, the mobility of the semiconductor device is improved. Further, by using the diffusion barrier layer, the integrity of the gate oxide is retained, resulting in a robust semiconductor device with a low on-state resistance.

Abstract: Embodiments of the invention include a microelectronic device that includes a substrate having transistor layers and interconnect layers including conductive layers to form connections to transistor layers. A capacitive bump is disposed on the interconnect layers. The capacitive bump includes a first electrode, a dielectric layer, and a second electrode. In another example, an inductive bump is disposed on the interconnect layers. The inductive bump includes a conductor and a magnetic layer that surrounds the conductor.

Abstract: The present technology relates to an electronic substrate that achieves a reduction in the size of a substrate and enables a void risk in an underfill to be reduced, and an electronic apparatus. An electronic substrate in one aspect of the present technology includes: an electronic chip that is placed above a substrate; an electrode that exists between the substrate and the electronic chip and electrically connects the substrate and the electronic chip; an underfill with which a space between the substrate and the electronic chip is filled so that the electrode is sealed and protected; a protection target to be protected from inflow of the underfill, the protection target being formed on the substrate; and an underfill inflow prevention unit that is formed in the substrate so as to surround an entirety or a portion of the protection target. The present technology is applicable to, for example, a solid-state image sensor.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate that includes a surface exposing a first film containing silicon, oxygen, carbon and nitrogen and having an oxygen atom concentration higher than a silicon atom concentration, which is higher than a carbon atom concentration, which is equal to or higher than a nitrogen atom concentration; and changing a composition of a surface of the first film so that the nitrogen atom concentration becomes higher than the carbon atom concentration on the surface of the first film, by supplying a plasma-excited nitrogen-containing gas to the surface of the first film.

Abstract: A main carrier wafer includes a first integrated network of electronic connections between front and back faces. A first electronic chip is mounted to the front face of the main carrier wafer and connected to the network of electronic connections of the main carrier wafer. A secondary carrier wafer includes a platform that extends over the first chip and a base the protrudes backwards with respect to the platform to a back end face facing the main wafer. A second integrated network of electronic connections is provided within the secondary carrier wafer. A second electronic chip is mounted on top of the platform and connected to the second integrated network. The second integrated network is further connected to the main carrier wafer at the back end face.

Abstract: A method of forming a magnetic tunnel junction (MTJ) containing device is provided in which a patterned sacrificial material is present atop a MTJ pillar that is located on a bottom electrode. A passivation material liner and a dielectric material portion laterally surround the MTJ pillar and the patterned sacrificial material. The patterned sacrificial material is removed from above the MTJ pillar and replaced with a top electrode. A seam is present in the top electrode. The method mitigates the possibility of depositing resputtered conductive metal particles on a sidewall of the MTJ pillar. Thus, improved device performance, in terms of a reduction in failure mode, can be obtained.