Abstract: A method for manufacturing a semiconductor device includes: forming a photocatalytic layer and an organic compound layer in contact with the photocatalytic layer over a substrate having a light transmitting property; forming an element forming layer over the substrate having the light transmitting property with the photocatalytic layer and the organic compound layer in contact with the photocatalytic layer interposed therebetween; and separating the element forming layer from the substrate having the light transmitting property after the photocatalytic layer is irradiated with light through the substrate having the light transmitting property.

Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.

Abstract: Implementations described herein generally relate to processes for the fabrication of semiconductor devices in which a self-assembled monolayer (SAM) is used to achieve selective area deposition. Methods described herein relate to alternating SAM molecule and hydroxyl moiety exposure operations which may be utilized to form SAM layers suitable for blocking deposition of subsequently deposited materials.

Abstract: The present disclosure generally relates to printed circuit boards or printed circuit board assemblies for fiber optic communications. In one example, a method may include coupling at least one optoelectronic component to a surface of a printed circuit board. The method may include lasering the surface of the printed circuit board to form a laser-roughened area on the surface of the printed circuit board. The method may include coupling an optical component to the printed circuit board at the laser-roughened area on the surface of the printed circuit board.

Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

Abstract: A display panel and a fabricating method thereof are provided. The display panel has a substrate, an active layer, an insulating layer, a first metal layer, an organic insulating layer, and a second metal layer. The display panel and the fabricating method thereof use an organic material as a dielectric insulating layer to reduce a problem that cracking is prone to occur when the display panel accumulates a large stress during bending. A minimum pore size of a through hole of the organic material is greater than that of an inorganic material, which is disadvantageous of a high-pixel-density display panel. Therefore, a first contact portion and a second contact portion of the first metal layer are electrically connected to the active layer, and a source electrode and a drain electrode of the second metal layer are electrically connected to the first/second contact portion respectively for the high-pixel-density display panel.

Abstract: A method of imaging infrared light is provided which comprises: exciting ultrasonic waves in a metal pillar (e.g., Cu pillar); measuring the Time-of-Flight (ToF) of the ultrasonic wave in the waveguide; whereas the ToF is a function of incident Infrared light energy on the waveguide, and reporting the infrared light energy to capture an image. An apparatus of imaging infrared light is provided which comprises: a transducer; a waveguide coupled with the transducer; and a pixel electronic circuit coupled to the transducer, wherein the transducer includes one or more of: PZT, LiNb, AlN, or GaN.

Abstract: The present invention provides a patterned structure for an electronic device and a manufacturing method thereof. The patterned structure includes a patterned layer, a blocking structure, a cantilever structure, and a connection structure. The patterned layer is disposed on a substrate. The blocking structure is disposed on the substrate at one side of the patterned layer, wherein a thickness of the blocking structure is smaller than a thickness of the patterned layer. The cantilever structure is disposed on the substrate and located between the patterned layer and the blocking structure. The cantilever structure is connected with the patterned layer and the blocking structure. The connection structure is connected between the patterned layer and the substrate at one side of the patterned layer, and located on the cantilever structure and the blocking structure.

Abstract: A method for manufacturing an optical wafer may include coating multiple optical components with a substrate. The multiple optical components may include a light emitting component and a light detecting component, and each of the optical components may include one or more electrical connections. The method may also include depositing a redistribution layer onto at least one of the electrical connections, wherein the redistribution layer routes the electrical connection within the optical wafer to an external connection. The method may also include depositing a passivation layer over the redistribution layer and depositing a dark photoresist layer on at least the passivation layer. The photoresist layer may operatively reduce optical interference between at least one light emitting component and at least one light detecting component.

Abstract: A process of depositing zirconium oxide (ZrO2) layers possessing dual properties of anti-reflection and passivation of silicon surfaces, including passivation of n-type and p-type silicon substrates. To grow a ZrO2 anti-reflection passivation layer, a precursor layer of zirconium oxide is spun on a silicon surface then dried, pyrolyzed and fired at suitable contact firing conditions, avoiding additional deposition. Thermal annealing in a hydrogen environment improves passivation quality of ZrO2 layer to a level 3-4 times higher than that of fired films alone. ZrO2 dielectric passivation layers exhibit improved passivation quality after illumination due to photo-enhanced passivation and higher passivation quality at higher thermal budget suitable for screen printed metal contact firing, unlike standard PECVD deposited passivation layers. The method is adaptable for fabrication of silicon solar cells and other structures utilizing passivated layers.

Abstract: A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying a stress compensating oxide layer to each of two heterogeneous wafers, applying at least one bonding oxide layer to at least one of the two heterogeneous wafers, chemical-mechanical polishing the at least one bonding oxide layer, and low temperature bonding the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafers having a stress compensating oxide layer and at least one bonding oxide layer applied to at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded together to form the multi-layer wafer.

Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips with interconnect structures are disclosed. LED chips are provided that include first interconnects electrically coupled to an n-type layer and second interconnects electrically connected to a p-type layer. Configurations of the first and second interconnects are provided that may improve current spreading by reducing localized areas of current crowding within LED chips. Various configurations are disclosed that include collectively formed symmetric patterns of the first and second interconnects, diameters of certain ones of either the first or second interconnects that vary based on their relative positions in LED chips, and spacings of the second interconnects that vary based on their distances from the first interconnects. In this regard, LED chips are disclosed with improved current spreading as well as higher lumen outputs and efficiencies.

Abstract: A Chip-on-Board (COB) display module is provided, which includes a Printed Circuit Board (PCB) a plurality of Light-Emitting Diode (LED) luminous units, a packaging adhesive layer and a light shielding layer wherein the plurality of LED luminous units are mounted and fixed on the PCB, the packaging adhesive layer covers the PCB and wraps the LED luminous units thereon, a liquid passage is provided in the packaging adhesive layer between every two adjacent LED luminous units, and the light shielding layer fills the liquid passage. The COB display module further includes a reflecting layer, and the reflecting layer covers two sidewalls of the liquid passage, and is positioned between the packaging adhesive layer and the light shielding layer. A manufacturing method for the COB display module is also disclosed.

Abstract: A method of forming a three-dimensional transistor device. The method may include providing a transistor structure, where the transistor structure includes a fin assembly, a gate assembly, the gate assembly disposed over the fin assembly and comprising a plurality of gates, a liner layer, disposed over the plurality of gates, and an isolation layer, disposed subjacent the liner layer. The method may also include directing first angled ions at the transistor device, wherein a first altered liner layer is created in the liner layer, wherein, in the presence of a liner-removal etchant, the liner layer exhibits a first etch rate, the first altered liner layer exhibits a second etch rate, greater than the first etch rate.

Abstract: The present disclosure provides a method for making a thin film transistor (TFT), a TFT, a back plate and a display device. The TFT includes: a gate electrode, a source, a drain, a dielectric layer and an active layer on the dielectric layer. The active layer includes at least one a-Si area and at least one p-Si area. This can reduce leakage current and reduce the technical complexity of the large-channel TFT.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a first dielectric layer having a metal layer therein; forming a second dielectric layer on the first dielectric layer and the metal layer; forming a metal oxide layer on the second dielectric layer; performing a first etching process by using a chlorine-based etchant to remove part of the metal oxide layer to forma via opening and expose the second dielectric layer; forming a block layer on sidewalls of the metal oxide layer and a top surface of the second dielectric layer; and performing a second etching process by using a fluorine-based etchant to remove part of the block layer and part of the second dielectric layer for exposing a top surface of the metal layer.

Abstract: A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.

Abstract: A semiconductor structure including at least one integrated circuit component is provided. The at least one integrated circuit component includes a first semiconductor substrate and a second semiconductor substrate electrically coupled to the first semiconductor substrate, wherein the first semiconductor substrate and the second semiconductor substrate are bonded through a first hybrid bonding interface, and at least one of the first semiconductor substrate or the second semiconductor substrate includes at least one first embedded capacitor.

Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2/capping layer configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance×area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable net magnetoresistive ratio (DRR). Moreover, magnetizations in first and second pinned layers, PL1 and PL2, respectively, are aligned antiparallel to enable a lower critical switching current than when in a parallel alignment. An oxide capping layer having a RACAP is formed on PL2 to provide higher PL2 stability. The condition RA1<RA2 and RACAP<RA2 is achieved when TB1 and the oxide capping layer have one or both of a smaller thickness and a lower oxidation state than TB2, are comprised of conductive (metal) channels in a metal oxide or metal oxynitride matrix, or are comprised of a doped metal oxide or doped metal oxynitride layer.

Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.