Abstract: A storage system in one embodiment comprises a host processor, a volatile memory associated with the host processor, and a solid-state storage device comprising a non-volatile memory. The host processor is configured to detect a particular power condition, such as a power failure condition, and responsive to the detected power condition to direct the copying of data from the volatile memory associated with the host processor to the non-volatile memory of the solid-state storage device. In conjunction with directing the copying of data from the volatile memory associated with the host processor to the non-volatile memory of the solid-state storage device, the host processor further directs the solid-state storage device to enter an enhanced write bandwidth operating mode in which the solid-state storage device temporarily at least partially suspends at least one specified background process that would otherwise tend to restrict an achievable write bandwidth of the solid-state storage device.

Abstract: A computer-implemented data collection and analysis method comprises receiving from a client computing device, at least one data analysis datapoint, adding the received at least one data analysis datapoints to a data structure, and adding an additional data analysis datapoint to the data structure, storing, in a data repository, the data structure further comprising a data processing result, maintaining at least partially consistent copies of the data structure across the plurality of host computers, in response to a request regarding an operation from the client computing device, retrieving the data processing result from the data repository, and providing the data processing result using routing information to the client computing device. The data structure comprises an index of data analysis datapoints from the plurality of host computing devices. A portion of the additional data analysis datapoint is added to the data value to generate a data processing result.

Abstract: Provided are systems and methods for a location-aware, self-configuring peripheral device. In some implementations, the peripheral device may include two or more personalities. In these implementations, a personality enables the peripheral device to provide a service. In some implementations, the peripheral device may be configured to receive a configuration cycle. In some implementations, the peripheral device may further select a personality from among two or more personalities. The peripheral device may use information derived from the configuration cycle to make this selection. Selecting a personality may further include configuring the peripheral device according to the selected personality.

Abstract: An input/output control device includes: a bus connected to an input interface; a plurality of circuit selectors which are connected to the bus and to which validity or invalidity of an operation is set, each circuit selector outputting a signal of the bus when the validity is set; a plurality of logical circuits which are respectively provided to each of the circuit selectors, each logical circuit performing a logical operation when a signal is inputted from the circuit selector; an output selector which is connected to the bus and to which validity or invalidity of an operation is set, the output selector outputting a signal of the bus to an output interface when the validity is set; and an operation part which validates or invalidates the plurality of circuit selectors or the output selector based on an operation order of the plurality of circuit selectors and the output selector.

Abstract: According to one embodiment, a computer system includes a host computer, and a storage device coupled to the host computer. The host computer has a user-space device driver of the storage device in a user space of a host operating system (OS). The user-space device driver is configured to handle I/O operations to and from the storage device based on an application running on the host computer.

Abstract: Systems, methods, and computer-readable storage media for automatic hardware recovery. In some examples, a system can receive a notification of a device failure of a peripheral component interconnect express device associated a node. The system can also receive a first request to disconnect a link between the peripheral component interconnect express device and the node, and a second request to connect, after disconnecting the link, a replacement peripheral component interconnect express device with the node. The system can then reconfigure a peripheral component interconnect express switch fabric to disconnect the link between the peripheral component interconnect express device and the node, and connect the replacement peripheral component interconnect express device with the node.

Abstract: The present invention provides a method for managing the wiring and growth of a direct interconnect network implemented on a torus or higher radix interconnect structure based on an architecture that replaces the Network Interface Card (NIC) with PCIe switching cards housed in the server. Also provided is a passive patch panel for use in the implementation of the interconnect, comprising: a passive backplane that houses node to node connectivity for the interconnect; and at least one connector board plugged into the passive backplane comprising multiple connectors. The multiple connectors are capable of receiving an interconnecting plug to maintain the continuity of the torus or higher radix topology when not fully enabled. The PCIe card for use in the implementation of the interconnect comprises: at least 4 electrical or optical ports for the interconnect; a local switch; a processor with RAM and ROM memory; and a PCI interface.

Abstract: A system and method are provided for generating interrupts in a computer system using limited interrupt virtualization hardware. A peripheral component interconnect express (PCIe) device atomically sets one or more bits in a posted interrupt vector (PIV) of a target central processing unit (CPU), and sends an interrupt to the target CPU, the interrupt notifying the target CPU of changes to the PIV. Atomically setting the one or more bits may include executing a compare-and-swap function, executing a fetch-and-add instruction to increment a DWORD corresponding to the one or more bits in the PIV by a value of 2 ^ (b mod 32), using PCIe byte enables to write to a single byte in the PCIe address space that contains the one or more bits, using a helper CPU, performing a PCIe swap to the PIV, or storing the PIV in a memory of the PCIe device.

Abstract: Methods, systems, and computer storage mediums including a computer program product for managing data in a computing network are provided. One method includes registering a plurality of buffers with a work queue in a server and assigning ownership to each of the plurality of buffers to a different working thread in a plurality of working threads. The method further includes continuously polling, by a polling thread, the work queue to determine when work requests are received by the work queue, upon receipt of each work request, determining which buffer among the plurality of buffers each work request is associated, and performing each work request on each respective associated buffer by a working thread among the plurality of working threads that owns each respective associated buffer. One system includes a processor for performing the above method and one computer storage medium includes computer code for performing the above method.

Abstract: A method, system and computer program product are disclosed for routing data packet in a computing system comprising a multidimensional torus compute node network including a multitude of compute nodes, and an I/O node network including a plurality of I/O nodes. In one embodiment, the method comprises assigning to each of the data packets a destination address identifying one of the compute nodes; providing each of the data packets with a toio value; routing the data packets through the compute node network to the destination addresses of the data packets; and when each of the data packets reaches the destination address assigned to said each data packet, routing said each data packet to one of the I/O nodes if the toio value of said each data packet is a specified value. In one embodiment, each of the data packets is also provided with an ioreturn value used to route the data packets through the compute node network.

Abstract: A dynamically configurable device including a connector configured to detect a first status of an interface selection mechanism, and a first Serializer De-serializer (SerDes) configured to drive a first selected interface from among a plurality of interfaces based on the first status. In response to the first status having a first state, the first selected interface is a first interface that causes the dynamically configurable device to present as a first type of device, and in response to the first status having a second state, the first selected interface is a second interface that causes the dynamically configurable device to present as a second type of device.

Abstract: Embodiments herein relate to assigning processors to a memory mapped configuration. The processors having access to different buses of a Peripheral Component Interconnect (PCI) segment are quiesced. The quiesced processors are assigned a memory mapped configuration.

Abstract: A system includes a management controller for managing a plurality of computing platforms. The management controller includes a processor, a physical network interface controller (NIC), a volatile memory, and a non-volatile memory storing computer executable code. The computer executable code, when executed at the processor, is configured to: provide a plurality of firmware instances, each corresponding to a respective one of the computing platforms; configure a plurality of virtual NICs (VNICs), each of the VNICs corresponding to a respective one of the firmware instances, wherein the VNICs share network resource provided by the physical NIC; and for each of the firmware instances, in response to a communication command to transmit data through the corresponding VNIC, transmit the data through the physical NIC.

Abstract: Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instruction or return from asynchronous interrupt, is to be executed. Based on determining that such an instruction is to be executed, a predicted address is determined for the selected instruction, which is the address to which processing transfers in order to provide the requested services. Then, fetching of instructions beginning at the predicted address prior to execution of the selected instruction is commenced. Further, speculative state relating to a selected instruction, including, for instance, an indication of the privilege level of the selected instruction or instructions executed on behalf of the selected instruction, is predicted and maintained.

Abstract: Two channels of a main CPU channel and a sub CPU channel each including a reception channel and a transmission channel, and performing a data transfer by a DMA in accordance with a descriptor are provided, a channel switching part selects the main CPU channel or the sub CPU channel in accordance with information set at a mode setting register, and performs a switching of channels at a boundary of a packet to be transferred to thereby enable the switching of channels without interrupting a DMA operation.

Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.

Abstract: A control element for a household appliance includes an antenna for communicating with an external data source. The antenna can be formed by a cap which is connected to a housing of the control element and is retractable in relation to the housing by a retraction mechanism accommodated in the housing. A transmit/receive unit is supported by the cap and is connected to flexible conductor paths for conveying received or transmitted data.

Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

Abstract: A data transmission system and a transmission method thereof are provided. The data transmission system includes a first electronic apparatus and a second electronic apparatus. The first electronic apparatus includes a first clock pin and a first data pin. The second electronic apparatus includes a second clock pin and a second data pin. In a connecting detection mode, the first electronic apparatus transmits a first detection signal to the first clock pin and drives the first data pin to a reference logic level. The second electronic apparatus transmits a second detection signal to the second clock pin and drives the second data pin to the reference logic level. The first electronic apparatus determines whether the first and the second electronic apparatuses are connected to each other according to whether at least one of signals on the first clock pin and on the first data pin is varied or not.

Abstract: A control unit monitors a number of transfer ready operations and a number of retry operations during a monitoring period during communication with a plurality of channels. Based, on the monitoring, a number of buffer credits for communication with the plurality of channels is adjusted.