Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

Abstract: A method is provided in one example embodiment and includes receiving by a network element a request from a network device connected to the network element to update a shared resource maintained by the network element; subsequent to the receipt, identifying a Base Address Register Resource Table (“BRT”) element assigned to a Peripheral Component Interconnect (“PCI”) adapter of the network element associated with the network device, wherein the BRT points to the shared resource; changing an attribute of the identified BRT from read-only to read/write to enable the identified BRT to be written by the network device; and notifying the network device that the attribute of the identified BRT has been changed, thereby enabling the network device to update the shared resource via a Base Address Register (“BAR”) comprising the identified BRT.

Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.

Abstract: A shared counter resource, such as a register, is disclosed in the hardware, where the register representing how much free space there is in the command queue is accessible to one or more processing elements. When a processing element reads the “reservation” register, the hardware automatically decrements the available free space by a preconfigured amount (e.g., 1) and returns the value of the free space immediately prior to the read/reservation. If the read returns 0 (or a number less than the preconfigured amount), there was insufficient free space to satisfy the request. In the event there was insufficient space to satisfy the request the reservation register may be configured to reserve however much space was available or to not reserve any space at all. Any number of processing elements may read these registers and various scenarios are described where the input and output queues are accessible via various processing elements.

Abstract: A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.

Abstract: A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.

Abstract: A method for outputting reliably predictable instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor, and out of that set, identifying a branch instruction having a series of subsequent frequently executed branch instructions that form a reliably predictable instruction sequence. The reliably predictable instruction sequence is stored into a buffer. On a subsequent hit to the branch instruction, the reliably predictable instruction sequence is output from the buffer.

Abstract: In a normal, non-loop mode a uOp buffer receives and stores for dispatch the uOps generated by a decode stage based on a received instruction sequence. In response to detecting a loop in the instruction sequence, the uOp buffer is placed into a loop mode whereby, after the uOps associated with the loop have been stored at the uOp buffer, storage of further uOps at the buffer is suspended. To execute the loop, the uOp buffer repeatedly dispatches the uOps associated with the loop's instructions until the end condition of the loop is met and the uOp buffer exits the loop mode.

Abstract: Provided are an apparatus and method for providing instructions for a heterogeneous processor having heterogeneous components supporting different data widths. Respective data widths of operands and connections in a data flow graph are determined by using type information of operands. Instructions, to be executed by the heterogeneous processor, are provided based on the determined data widths.

Abstract: A media source device includes media files in either original source format or in alternative digital formats, based on a content descriptor indicated by a client device from a plurality of content descriptors generated to represent possible transcodings of the source format. In the alternative, a media source device can receive a client device report and subsequent request for a media file. The media source device can send the media file to the client device in a particular digital format based on whether the content descriptor corresponding to the media file is compatible or incompatible with the client device. The bit rate used to send the media file to the client device can be adjusted based on the available transmit bit rate.

Abstract: Systems, methods, circuits and computer-readable mediums for system internal latency measurements in realtime applications are disclosed. In some implementations, a trigger signal is selected from a plurality of trigger signals for interrupting a processor of an integrated circuit system. The trigger signal includes a pulse having width. The system detects a rising edge of the pulse and starts a counter. The system detects a falling edge of the pulse and stops the counter. The system then compares a count of the counter with first and second values stored in first and second registers, respectively. The first value represents a minimum pulse width and the second value represents a maximum pulse width. The count is stored in the first or second register based on a result of the comparing.

Abstract: A language-based model to support asynchronous operations set forth in a synchronous syntax is provided. The asynchronous operations are transformed in a compiler into an asynchronous pattern, such as an APM-based pattern (or asynchronous programming model based pattern). The ability to compose asynchronous operations comes from the ability to efficiently call asynchronous methods from other asynchronous methods, pause them and later resume them, and effectively implementing a single-linked stack. One example includes support for ordered and unordered compositions of asynchronous operations. In an ordered composition, each asynchronous operation is started and finished before another operation in the composition is started. In an unordered composition, each asynchronous operation is started and completed independently of the operations in the unordered composition.

Abstract: A method is provided for preserving redundant copies of metadata in a data storage system employing de-duplication. The method includes (a) creating metadata describing a file of a file system stored on the data storage system, (b) buffering the metadata within a metadata buffer of system memory of the data storage system, (c) sending contents of the metadata buffer from system memory to transmission circuitry of the data storage system, (d) directing the transmission circuitry to store the contents of the metadata buffer to a first location of persistent storage of the data storage system, and (e) directing the transmission circuitry to store a modified version of the contents of the metadata buffer to a second location of persistent storage of the data storage system, the first location being different from the second location. A computerized apparatus and a computer program product are also provided for performing a similar method.

Abstract: A wireless transmission and video integrated apparatus includes a hub module, a video module and a wireless module. The hub module includes a hub unit, a first expansion interface, a second expansion interface and a transmission interface. The video module includes a first connection interface, an image processing unit, an image acquisition unit and a microphone unit. The video module is electrically connected to the first expansion interface of the hub module through the first connection interface. The wireless module includes a second connection interface, a wireless communication unit and an antenna unit. The wireless module is electrically connected to the second expansion interface of the hub module through the second connection interface. The video module and the wireless module are integrated as a whole through the hub module, and then electrically connected to an electronic apparatus through the transmission interface to help with the assembly.

Abstract: Instructions are grouped into instruction groups based on optimizations that may be performed. An instruction is obtained, and a determination is made as to whether the instruction is to be included in a current instruction group or another instruction group. This determination is made based on whether the instruction is a candidate for optimization, such as decode time instruction optimization. If it is determined that the instruction is to be included in another group, then the other group is formed to include the instruction.

Abstract: Instructions are grouped into instruction groups based on optimizations that may be performed. An instruction is obtained, and a determination is made as to whether the instruction is to be included in a current instruction group or another instruction group. This determination is made based on whether the instruction is a candidate for optimization, such as decode time instruction optimization. If it is determined that the instruction is to be included in another group, then the other group is formed to include the instruction.

Abstract: A processor and method for fusing together an arithmetic instruction and a branch instruction. The processor includes an instruction fetch unit configured to fetch instructions. The processor may also include an instruction decode unit that may be configured to decode the fetched instructions into micro-operations for execution by an execution unit. The decode unit may be configured to detect an occurrence of an arithmetic instruction followed by a branch instruction in program order, wherein the branch instruction, upon execution, changes a program flow of control dependent upon a result of execution of the arithmetic instruction. In addition, the processor may further be configured to fuse together the arithmetic instruction and the branch instruction such that a single micro-operation is formed. The single micro-operation includes execution information based upon both the arithmetic instruction and the branch instruction.

Abstract: A method of storing data in a storage system is provided. The method includes writing data, from a virtual machine in a compute node, to a primary storage coupled to the virtual machine and sending a first copy of the data from the compute node to a data node. The method includes writing the first copy of the data from the compute node to an intermediate storage coupled as direct attached storage to the data node, and writing a second copy of data from the intermediate storage to a secondary storage, wherein at least one method operation is performed by a processor. A storage system is also provided.

Abstract: A processor may efficiently implement register renaming and checkpoint repair even in instruction set architectures with large numbers of wide (bit-width) registers by (i) renaming all destination operand register targets, (ii) implementing free list and architectural-to-physical mapping table as a combined array storage with unitary (or common) read, write and checkpoint pointer indexing and (iiii) storing checkpoints as snapshots of the mapping table, rather than of actual register contents. In this way, uniformity (and timing simplicity) of the decode pipeline may be accentuated and architectural-to-physical mappings (or allocable mappings) may be efficiently shuttled between free-list, reorder buffer and mapping table stores in correspondence with instruction dispatch and completion as well as checkpoint creation, retirement and restoration.

Abstract: In a numerical control system in which a numerical controller is connected with a plurality of amplifiers via a daisy-chain serial bus, these amplifiers are grouped into a first group and a second group, and connected in an order of the amplifiers of the first group and the amplifiers of the second group from the numerical controller. Further, a communication cycle in the communication between the numerical controller and the amplifiers of the second group is set n times (n is an integer of 2 or larger) as large as a communication cycle of the first group.