Abstract: A configuration controller for and a method of controlling a configuration of a circuitry are provided. The configuration controller comprises an input, a selection checker, a data selector and an output. The input receives an input configuration selection signal which is encoded according to a specific encoding scheme. The selection checker checks a correctness of the received input configuration selection signal and provides to the data selector a selection signal which indicates a specific configuration selection if the input configuration selection data is correct or indicates a default configuration selection if the input configuration selection signal is incorrect according to the specific encoding scheme. The data selector selects configuration data from its internal configuration data storage in accordance with the selection signal and provides the selected configuration data to the output.

Abstract: An interface unit is provided for the arrangement between a bus system, to which a processor unit and a data memory are connectable, and a data transporting unit, in particular a network processor, are described. The interface unit carries out a direct memory access to the data memory as a function of an identifier (chid) previously agreed upon between an application and the data transporting unit.

Abstract: Embodiments of the present invention may include a data processing system comprising a processing execution block to execute instructions stored in an instruction queue, a programmable hardware accelerator, and a controller programmed to monitor the instruction queue to detect a first type of instructions stored in the instruction queue, reprogram the programmable hardware accelerator to execute the first type of instructions, and transmit the first type of instructions to the programmable hardware accelerator to be executed.

Abstract: A device for matching, in input data, a regular expression with back-references, represented by a finite-state machine (FSM). The device comprises a plurality of parallel processing elements (PPEs), an interconnection network for interconnecting the PPEs with each other, and a memory for receiving and storing input data. The PPEs process the input data stored in the memory, based on backtracking to process the back-references, and implement FA next state logic to generate new active FA configurations or mark themselves as available to receive active FA configurations. The interconnection network retrieves active FA configurations from the PPEs and allocates the active FA configurations to available PPEs. The PPEs are configured to match a regular expression in the input data.

Abstract: A synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation demodulation is disclosed. A method includes receiving multiple bits to be transmitted, encoding the multiple bits to generate a multi-bit signal that represents the multiple bits, and transmitting, via a synchronous interface, the multi-bit signal during a time period that corresponds to one-half of a cycle of a synchronization signal.

Abstract: Communicating among multiple sets of multiples cores includes: buffering messages in first buffer associated with a first set of multiple cores; buffering messages in a second buffer associated with a second set of multiple cores; and transferring messages over communication circuitry from cores not in the first set to the first buffer, and to transferring messages from cores not in the second set to the second buffer. A first core of the first set sends messages corresponding to multiple types of instructions to a second core of the second set through the communication circuitry. The second buffer is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores in the first set at the same time, and still have enough storage space for one or more instructions of a first type.

Abstract: A channel of a host computational device sends a command to transfer data to a control unit included in a storage controller. The channel of the host computational device receives a number of buffer credits from the control unit for communication with the control unit, where the number of buffer credits that is received is based on the control unit monitoring a number of transfer ready operations and a number of retry operations during a monitoring period while communicating with a plurality of channels that includes the channel.

Abstract: In one general aspect, a main printed circuit board (PCB) card can include a System on a Chip (SoC) configured to run an operating system stored on the main PCB card, at least one dynamic random access memory (DRAM) device and at least one non-volatile memory device each configured for use by the SoC, and at least one connector. The main PCB card can be configured to be interchangeably interfaced with multiple types of shell computing devices by way of a slot included in a shell computing device. The slot can be configured to accommodate the main PCB card. Each type of shell computing device can be of a different form factor. Each form factor can be representative of a different type of computing device. The at least one connector can be configured to be plugged into a mating connector included in a shell computing device.

Abstract: A disassembler receives instructions and disassembles them into a plurality of separate opcodes. The disassembler creates a table identifying boundaries between each opcode. Each opcode is written to memory in an opcode-by-opcode manner by atomically writing standard blocks of memory. Debug break point opcodes are appended to opcode to create a full block of memory when needed. The block of memory may be thirty-two or sixty-four bits long, for example. Long opcodes may overlap two or more memory blocks. Debug break point opcodes may be appended to a second portion of the long opcode to create a full block of memory. A stream fault interceptor identifies when a requested data page is not available and retrieving the data page.

Abstract: Embodiments of the claimed subject matter are directed to methods and a system that allows an application comprising a single code set under the COBOL Programming Language to execute in multiple platforms on the same multi-platform system (such as a mainframe). In one embodiment, a single code set is pre-compiled to determine specific portions of the code set compatible with the host (or prospective) platform. Once the code set has been pre-compiled to determine compatible portions, those portions may be compiled and executed in the host platform. According to these embodiments, an application may be executed from a single code set that is compatible with multiple platforms, thereby potentially reducing the complexity of developing the application for multiple platforms.

Abstract: In computing scenarios involving multiple computational units, an enclosure (e.g., a rack or server cabinet) may store the units and provide resources such as shared power and network connectivity. Additionally, the components of the units may communicate through a Serial Attached SCSI (SAS) bus, but many such enclosures provide little or no integration with the SAS buses, thus entailing extensive SCSI cabling. Presented herein are architectures for enclosures presenting a set of slots for trays storing respective computing blades, where such trays include SAS connectors that connect directly (i.e., without cabling) with connectors on a midplane that interconnects the blades into a SAS bus featuring at least one integrated SAS expander. Additional architectural variations involve providing SAS expander on one or both of the midplane and the blades; grouping blades into subsets having distinct SAS buses; and interconnecting the SAS buses and expanders of multiple midplanes in the enclosure.

Abstract: Migrating MMIO from a source I/O adapter of a computing system to a destination I/O adapter of the computing system, includes: collecting, by a hypervisor of the computing system, MMIO mapping information, wherein the hypervisor supports operation of a logical partition executing and the logical partition is configured for MMIO operations with the source I/O adapter through a MMU of the computing system utilizing the MMIO mapping information; placing, by the hypervisor, the destination I/O adapter in an error state; configuring, by the hypervisor, the MMU for MMIO with the logical partition utilizing the MMIO mapping information collected by the hypervisor; and enabling the destination I/O adapter to recover from the error state.

Abstract: When providing a user with native access to at least a portion of device hardware, the user can be prevented from modifying firmware and other configuration information by controlling the mechanisms used to update that information. In some embodiments, an asymmetric keying approach can be used to encrypt or sign the firmware. In other cases access can be controlled by enabling firmware updates only through a channel or port that is not exposed to the customer, or by mapping only those portions of the hardware that are to be accessible to the user. In other embodiments, the user can be prevented from modifying firmware by only provisioning the user on a machine after an initial mutability period wherein firmware can be modified, such that the user never has access to a device when firmware can be updated. Combinations and variations of the above also can be used.

Abstract: A group of low-level FIFOs may be logically bound together to form a super-FIFO. The super-FIFO may treat each low-level FIFO as a storage location. The super-FIFO may enable a push to (or a pop from) every low-level FIFO, simultaneously. The super-FIFO may enable a virtual channel (VC) to use the super-FIFO, bypassing a VC FIFO for the VC, removing several cycles of latency otherwise needed for enqueuing and dequeuing messages in the VC FIFO. In addition, the super-FIFO may enable bypassing of an arbiter, further reducing latency by avoiding a penalty of the arbiter.

Abstract: End-user software is used to select lists of values of control signals from a predetermined design of a processor, and a unique value of an opcode is assigned to each selected list of values of control signals. The assignments, of opcode values to lists of values of control signals, are used to create a new processor design customized for the end-user software, followed by synthesis, place and route, and netlist generation based on the new processor design, followed by configuring an FPGA based on the netlist, followed by execution of the end-user software in customized processor implemented by the FPGA. Different end-user software may be used as input to generate different assignments, of opcode values to lists of control signal values, followed by generation of different netlists. The different netlists may be used at different times, to reconfigure the same FPGA, to execute different end-user software optimally at different times.

Abstract: A remotely controlled electronic general switch in DC power electrical supply system(s), ensuring switching and control of current and supply voltage, has an electronic module. The module has a controller or processor connected (i) to the switching and measurement circuit, the controller and measurement circuit optionally being linked bidirectionally, the controller being configured such that, when it receives a voltage and current measurement of the measurement circuit, it is respectively able to verify whether the input voltage lies in a predetermined interval and to instruct current interruption by the switching circuit for a certain duration, as a function of the measured current value, and (ii) to the communication interface, the communication interface connected to the communication bus and controller optionally being linked bidirectionally, such that the controller can be programmed remotely.

Abstract: Examples are disclosed for establishing a secure destination address range responsive to initiation of a direct memory access (DMA) operation. The examples also include allowing decrypted content obtained as encrypted content from a source memory to be placed at a destination memory based on whether destination memory addresses for the destination memory fall within the secure destination address range.

Abstract: Aspects of the present invention include a port extender environment using the port extenders to dynamically select a data path. In embodiments of the present invention, each port extender can communicate data traffic to another port extender or to a host receiver. The communication path is selected in the port extender using a hashing system.

Abstract: Migrating MMIO from a source I/O adapter of a computing system to a destination I/O adapter of the computing system, includes: collecting, by a hypervisor of the computing system, MMIO mapping information, wherein the hypervisor supports operation of a logical partition executing and the logical partition is configured for MMIO operations with the source I/O adapter through a MMU of the computing system utilizing the MMIO mapping information; placing, by the hypervisor, the destination I/O adapter in an error state; configuring, by the hypervisor, the MMU for MMIO with the logical partition utilizing the MMIO mapping information collected by the hypervisor; and enabling the destination I/O adapter to recover from the error state.

Abstract: A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system.