Abstract: A semiconductor structure and fabrication method thereof are provided. The fabrication method includes: providing a base substrate including a substrate and a plurality of fins on the substrate; forming gate structures across the fins, to cover a portion of sidewalls of the fins and a portion of top surfaces of the fins; forming stress layers in the fins on sides of each gate structure; forming barrier layers on sidewalls of the gate structure; and forming doped regions by applying first ion implantation processes to the fins under the stress layers using the barrier layers as a mask.

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region. At least a majority of channel material of the dummy channel-material strings is replaced in the TAV region with insulator material and operative TAVs are formed in the TAV region. Other methods and structures independent of method are disclosed.

Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

Abstract: A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame.

Abstract: A semiconductor device includes an active region in a substrate, an isolation film defining the active region in the substrate, a gate trench extending across the active region and the isolation film and including a first trench in the active region and a second trench in the isolation film, a gate electrode including a main gate electrode and a pass gate electrode, the main gate electrode filling a lower part of the first trench, and the pass gate electrode filling a lower part of the second trench, a support structure on the pass gate electrode, the support structure filling an upper part of the second trench, a gate insulating film interposed between the isolation film and the pass gate electrode and between the support structure and the pass gate electrode.

Abstract: Provided is a Hall element which is reduced in asymmetrically generated offset voltage. A semiconductor device includes: a semiconductor layer of a first conductivity type having a Hall element forming region; an element isolation region of the first conductivity type having a concentration higher than a concentration of the semiconductor layer, the element isolation region being formed so as to surround the Hall element forming region; and a Hall element formed in the Hall element forming region and comprising a magnetism sensing portion of a second conductivity type which is higher in concentration than the semiconductor layer and which is kept apart from the element isolation region through the semiconductor layer.

Abstract: A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.

Abstract: A method for manufacturing optical sensor arrangements is provided. The method comprises providing at least two optical sensors on a carrier and providing a cover material on the side of the optical sensors facing away from the carrier. The method further comprises providing an aperture for each optical sensor on a top side of the cover material facing away from the carrier and forming at least one trench between the optical sensors from the carrier towards the top side of the cover material, the trench comprising inner walls. Moreover, the method comprises coating the inner walls with an opaque material, such that an inner volume of the trench is free of the opaque material, and singulating of the optical sensor arrangements along the at least one trench. Furthermore, a housing for an optical sensor is provided.

Abstract: Fabrication methods and resulting structures for single and double diffusion breaks are provided. Aspects include forming one or more fins on a substrate, the substrate including a first region and a second region, forming a plurality of sacrificial gate structures over channel regions associated with the one or more fins, forming a single diffusion break cavity in the first region of the substrate, forming a double diffusion break cavity in the second region of the substrate, depositing a first dielectric material in the single diffusion break cavity, and depositing a second dielectric material in the double diffusion break cavity.

Abstract: A spin current magnetization reversing element (100) includes a spin orbit torque wiring layer (101) that extends in one direction, a first ferromagnetic layer (102) that is formed on a first surface (101a) of the spin orbit torque wiring layer, and a first insulating layer (103) that is formed on a second surface (101b) on a side opposite to the first ferromagnetic layer (102) side on the surface of the spin orbit torque wiring layer. The first insulating layer (103) contains boron nitride or aluminum nitride.

Abstract: A semiconductor device includes a substrate, a die and multiple conductive traces. The die is mounted on the substrate. The conductive traces are routed on the substrate and connected to the die. The conductive traces at least include a plurality of first conductive traces and a plurality of second conductive traces. The second conductive traces are coupled to a predetermined voltage for providing a shielding pattern. The first conductive traces and the second conductive traces are disposed on the substrate in a substantially interlaced pattern.

Abstract: A modular photovoltaic system adapted for collecting light rays from a solar light source to generate electrical current, the system having a light-tracking solar collector adapted to collect the light rays, an edge-lit photovoltaic array, and a transport conduit adapted to transport the light rays to the edge-lit photovoltaic array. The edge-lit photovoltaic array has a plurality of edge-lit photovoltaic panels, each having a transparent diffusing pane positioned between two backing panels with inwardly directed photovoltaic surfaces. Each edge-lit photovoltaic panel perpendicularly contacts a lateral light distributor attached to the transport conduit, causing the transparent diffusing pane to illuminate the photovoltaic surfaces to generate electrical current. The light-tracking solar collector is adapted to rotate to remain oriented toward the solar light source.

Abstract: An integrated circuit device is disclosed, which integrated circuit device comprises at least a first external contact, a second external contact, and an input stage, connected with the external contacts and being configured to provide an internal operating voltage when an external voltage is applied to the external contacts. To allow easier handling at manufacture, test, assembly, and end use, the internal operating voltage has a predefined polarity, which predefined polarity is independent of the polarity of the external voltage.

Abstract: A manufacturing method of a vertical GaN-based semiconductor device having: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type impurity, which is lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, the method includes: implanting an n type dopant in a back surface of the GaN-based semiconductor substrate after forming of the MIS structure, and annealing the GaN-based semiconductor substrate after the implanting of the n type dopant.

Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor a silicon substrate having a silicon dioxide layer; an adhesion layer on the silicon dioxide layer, wherein the adhesion layer is a polar dielectric; a first electrode layer on the adhesion layer; a dielectric layer on the first electrode layer; and a second electrode layer on the dielectric layer. Other embodiments are disclosed.

Abstract: In an example, a memory cell may have an interface dielectric adjacent to a semiconductor, a tunnel dielectric adjacent to the interface dielectric, a charge trap adjacent to the tunnel dielectric, a blocking dielectric adjacent to the charge trap, and a control gate adjacent to the blocking dielectric.

Abstract: A white LED lamp including: a conductive portion; a light emitting diode chip mounted on the conductive portion, for emitting a primary light having a peak wavelength of 360 nm to 420 nm; a transparent resin layer including a first hardened transparent resin, for sealing the light emitting diode chip; and a phosphor layer covering the transparent resin layer, the phosphor layer being formed by dispersing a phosphor powder into a second hardened transparent resin, and the phosphor powder receiving the primary light and radiating a secondary light having a wavelength longer than that of the primary light. An energy of the primary light contained in the radiated secondary light is 0.4 mW/lm or less.

Abstract: A manufacturing method of integrated fan-out package includes following steps. First and second dies are provided on adhesive layer formed on carrier. Heights of first and second dies are different. First and second dies respectively has first and second conductive posts each having substantially a same height. The dies are pressed against adhesive layer to make active surfaces thereof be in direct contact with adhesive layer and conductive posts thereof be submerged into adhesive layer. Adhesive layer is cured. Encapsulant is formed to encapsulate the dies. Carrier is removed from adhesive layer. Heights of first and second conductive posts are reduced and portions of the adhesive layer is removed. First and second conductive posts are laterally wrapped by and exposed from adhesive layer. Top surfaces of first and second conductive posts are leveled. Redistribution structure is formed over adhesive layer and is electrically connected to first and second conductive posts.

Abstract: A method includes depositing a hardmask layer over a magnetoresistive (MR) structural layer formed on a substrate, the hardmask layer being formed from tungsten or a tungsten-based composition. A photoresist layer is deposited over the hardmask layer and is patterned to expose a first portion of the hardmask layer. A first etch process is performed to remove the first portion of the hardmask layer and expose a second portion of the MR structural layer and a dry etch process is performed to remove the second portion of the MR structural layer and produce an MR sensor structure. Following the dry etch process, a composite structure remains that includes the MR sensor structure and a hardmask section of the hardmask layer, the hardmask section overlying the MR sensor structure. A spacer formed from a protective, dielectric material layer may additionally be formed surrounding the composite structure.

Abstract: A semiconductor chip stack includes a first semiconductor chip, a second semiconductor chip, and a connection via which the first electrode and the second electrode are electrically connected to each other. The connection includes a first column and a second column. The first column is constituted by a material having a higher degree of activity with respect to heat than a material that constitutes the second column and is smaller in volume than the second column. Further, the connection has an aspect ratio of 0.5 or higher in a height direction.