Abstract: A semiconductor device includes a semiconductor substrate. A pad region is disposed on the semiconductor substrate. A micro bump is disposed on the pad region. The micro bump has a first portion on the pad region and a second portion on the first portion. The first portion and the second portion have different widths. The first portion has a first width and the second portion has a second width. The first width is larger or smaller than the second width. The micro bump includes nickel and gold. The semiconductor device also includes a passivation layer overlying a portion of the pad region.

Abstract: In a semiconductor device, a thinly-molded portion covering a whole of a heat dissipating surface portion of a lead frame and a die pad space filled portion are integrally molded from a second mold resin, because of which adhesion between the thinly-molded portion and lead frame improves owing to the die pad space filled portion adhering to a side surface of the lead frame. Also, as the thinly-molded portion is partially thicker owing to the die pad space filled portion, strength of the thinly-molded portion increases, and a deficiency or cracking is unlikely to occur.

Abstract: An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes one first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type. And an area of the first doped region is smaller than an area of the total second doped regions.

Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

Abstract: A light emitting device, has: a light emitting element; a substrate having a first main surface on which the light emitting element is mounted, and recesses on side surfaces adjacent to the first main surface, a cap covering the light emitting element, and having a light-transmissive member and a metal frame that supports the light-transmissive member and has side pieces extending toward the substrate from above the first main surface of the substrate, and tabs that is bended and extend from the side pieces and housed a part thereof in the recesses of the substrate.

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a memory cell on a homogeneous bottom electrode via (BEVA) top surface. In some embodiments, the integrated circuit comprises a conductive wire, a via dielectric layer, a via, and a memory cell. The via dielectric layer overlies the conductive wire. The via extends through the via dielectric layer to the conductive wire, and has a first sidewall, a second sidewall, and a top surface. The first and second sidewalls of the via are respectively on opposite sides of the via, and directly contact sidewalls of the via dielectric layer. The top surface of the via is homogenous and substantially flat. Further, the top surface of the via extends laterally from the first sidewall of the via to the second sidewall of the via. The memory cell is directly on the top surface of the via.

Abstract: An interconnect layout structure having air gaps includes a plurality of air gaps extended along a direction, and at least a first interconnect unit disposed in between the air gaps. The first interconnect unit includes a first conductive line, a first landing mark situated on the first conductive line and a first via structure situated on the first landing mark. The first via structure penetrates the first landing mark and is electrically connected to the first conductive line. And the first landing mark physically separates the air gaps arranged in a straight line.

Abstract: An integrated fan-out package includes a first and second dies, an encapsulant, and a redistribution structure. The first and second dies respectively has an active surface, a rear surface opposite to the active surface, and conductive posts on the active surface. The first and second dies are different types of dies. The active and rear surfaces of the first die are respectively leveled with the active and rear surfaces of the second die. Top surfaces of the conductive posts of the first and second dies are leveled. The conductive posts of the first and second dies are wrapped by same material. The encapsulant encapsulates sidewalls of the first and second dies. A first surface of the encapsulant is leveled with the active surfaces. The second surface of the encapsulant is leveled with the rear surfaces. The redistribution structure is disposed over the first die, the second die, and the encapsulant.

Abstract: Disclosed herein is an electronic circuit package includes a substrate having a power supply pattern, a first electronic component mounted on a first region of a front surface of the substrate, a mold resin that covers the front surface of the substrate so as to embed the first electronic component therein, and a laminated film covering an upper surface of the mold resin, the laminated film including a magnetic film and a first metal film. The first metal film is connected to the power supply pattern. The magnetic film is selectively thick on the first region.

Abstract: A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.

Abstract: A semiconductor device includes a substrate, a beam, a movable structural body, a first stopper member, a second stopper member and a third stopper member. The first stopper member is arranged with a first gap from the movable structural body in an in-plane direction. The second stopper member is arranged with a second gap from the movable structural body in an out-of-plane direction. The third stopper member is arranged opposite to the second stopper member with the movable structural body interposed therebetween in the out-of-plane direction, and is arranged with a third gap from the movable structural body. Consequently, there can be provided a semiconductor device in which excessive displacement of the movable structural body can be suppressed to thereby suppress damage to and breakage of the beam supporting the movable structural body, and a method of manufacturing the same.

Abstract: A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on the substrate, several metal wires electrically connected to the substrate and the sensor chip, a translucent layer corresponding in position to the sensor chip, a combining layer firmly fixing the translucent layer to the sensor chip, and a packaging compound. A top surface of the sensor chip has a sensing region and a spacing region around the sensing region. The sensor chip includes several connecting pads arranged on the top surface between at least part of the edges thereof and the spacing region. The translucent layer has a fixing region arranged outside a portion thereof adhered to the combining layer. The packaging compound covers the fixing region and the external sides of the sensor chip, the combining layer, and the translucent layer. Each metal wire is embedded in the combining layer and the packaging compound.

Abstract: A super junction MOSFET includes a substrate having a first conductive type, an epitaxial layer formed on the substrate, a set of pillars extending from the substrate through the epitaxial layer, the set of pillars being spaced apart from each other, a set of first wells, the set of first wells formed in the epitaxial layer to extend to an upper face of the epitaxial layer, and each of the set of first wells connected to at least one corresponding pillar of the set of pillars, a set of second wells of the first conductive type formed in the set of first wells, and a plurality of gate structures formed on the epitaxial layer, each extending in a first direction to have a stripe shape such that the gate structures are spaced apart from each other. Thus, the gate structure has a relatively small area to reduce an input capacitance of the super junction MOSFET.

Abstract: A microelectronic assembly can be made by forming a redistribution structure supported on a carrier, the structure including two or more layers of deposited dielectric material and two or more electrically conductive layers and including conductive features such as pads and traces electrically interconnected by vias. Electrical connectors may project above a second surface of the structure opposite an interconnection surface of the redistribution structure adjacent to the carrier. A microelectronic element may be attached and electrically connected with conductive features at the second surface, and a dielectric encapsulation can be formed contacting the second surface and surfaces of the microelectronic element. Electrically conductive features at the interconnection surface can be configured for connection with corresponding features of a first external component, and the electrical connectors can be configured for connection with corresponding features of a second external component.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on the substrate, several metal wires electrically connected to the substrate and the sensor chip, a translucent layer corresponding in position to the sensor chip, and an adhesive. A top surface of the sensor chip has a sensing region and a spacing region around the sensing region. The sensor chip includes several connecting pads arranged on a first portion of the top surface between the first edge and the spacing region, and a second portion of the top surface between the second edge and the spacing region is provided without any connecting pad. The width of the first portion is greater than that of the second portion. The adhesive covers the surrounding side of the sensor chip, the first portion, and the surrounding side of the translucent layer. Part of each metal wire is embedded in the adhesive.

Abstract: A semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first semiconductor region having a first conductivity type; and a second semiconductor region having a second conductivity type. The first semiconductor region is configured within the second semiconductor region and a plurality of crystal defects are formed in the second semiconductor region and at least part of the first semiconductor region is surrounded by the plurality of crystal defects. Therefore, recombination of charge carriers (electrons and holes) on a lateral direction and a longitudinal direction could be taken into account, and the switching time of the semiconductor device could be adequately decreased.

Abstract: A trenched base capacitive humidity sensor includes a plurality of trenches formed in a conductive layer, such as polysilicon or metal, on a substrate. The trenches are arranged parallel to the each other and partition the conductive layer into a plurality of trenched silicon electrodes. At least two trenched silicon electrodes are configured to form a capacitive humidity sensor. The trenches that define the trenched silicon electrodes can be filled partially (e.g., sidewall coverage) or completely with polyimide (Pl) or silicon nitride (SiN). A polyimide layer may also be provided on the conductive layer over the trenches and trenched electrodes. The trenches and the trenched silicon electrodes may have different widths to enable different sensor characteristics in the same structure.

Abstract: A device may include: a high-k layer disposed on a substrate and over a channel region in the substrate. The high-k layer may include a high-k dielectric material having one or more impurities therein, and the one or more impurities may include at least one of C, Cl, or N. The one or more impurities may have a molecular concentration of less than about 50%. The device may further include a cap layer over the high-k layer over the channel region, the high-k layer separating the cap layer and the substrate.

Abstract: There is provided a photodiode array including a semiconducting substrate and a plurality of photodiodes that are disposed at a surface of the substrate. Each photodiode is laterally spaced apart from neighboring photodiodes by a lateral substrate surface region. An optical interface surface of the substrate is arranged for accepting external input radiation. A plurality of electrically conducting fuses are disposed on the substrate surface. Each fuse is connected to a photodiode in the plurality of photodiodes. Each fuse is disposed at a lateral substrate surface region that is spaced apart from neighboring photodiodes in the plurality of photodiodes.