Abstract: An H bridge circuit that is connected to nodes N1 and N2 for a power source and nodes N3 and N4 for a motor includes: a PchMOS transistor that is disposed in an N-type first region and is connected between N1 and N3; an NchMOS transistor that is disposed in an N-type second region and is connected between N2 and N3; a PchMOS transistor that is disposed in an N-type third region and is connected between N1 and N4; and an NchMOS transistor that is disposed in an N-type fourth region and is connected between N2 and N4, in a P-type semiconductor substrate. The distance between the first region and third region is smaller than the distance between the first region and second region, smaller than the distance between the third region and fourth region, and smaller than the distance between the second region and fourth region.

Abstract: Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape.

Abstract: A photodetection element includes a semiconductor layer having, on one surface side, a periodic concave/convex structure that includes periodic convex portions and concave portions and converts light into surface plasmon, and a metal film provided on the one surface side of the semiconductor layer in correspondence to the periodic concave/convex structure, and in the periodic concave/convex structure, a Schottky junction portion that has a Schottky junction with the metal film is provided on a base end side of the convex portion, and a non-Schottky junction portion that does not have a Schottky junction with the metal film is provided on a distal end side of the convex portion.

Abstract: A semiconductor device includes a semiconductor member having a mesa structure in which a first semiconductor layer and a second semiconductor layer are laminated on each other and having a pn junction; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode connected to the first semiconductor layer on a lower surface of the first semiconductor layer, and having a capacitance of the insulating film when a reverse bias voltage is applied between the first electrode and the second electrode, so that a first voltage applied to the insulating film between a corner position (a first position) where the side surface of the insulating film disposed on the side surface of the mesa structure an

Abstract: An electronic circuit device includes a first electronic component having a set of first terminals disposed at a first pitch on a first surface, and a second electronic component having a set of second terminals disposed at a second pitch on a second surface facing the first surface of the first electronic component. The second pitch of the second terminals is set larger than the first pitch of the first terminals. By doing so, each of the second terminals is connected to at least one of the first terminals if a positional misalignment occurs. As a result, the electronic circuit device has an increased tolerance for positional misalignment between the first electronic component and the second electronic component and reduces the occurrence of connection failure.

Abstract: A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer.

Abstract: A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.

Abstract: A semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a first fin structure protruding from the first region of the semiconductor substrate and having a first portion and a second portion over the first portion. The semiconductor device structure also includes a liner structure including a first insulating liner layer and second insulating liner layer. The first insulating liner layer has a bottom portion covering the semiconductor substrate and a sidewall portion covering a sidewall of the first portion of the first fin structure. The second insulating liner layer is over the bottom portion and the sidewall portion of the first insulating liner layer and extends on a top surface of the sidewall portion of the first insulating liner layer. The semiconductor device structure also includes an isolation feature over the liner structure.

Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A contact structure is formed that includes a first contact arranged over a source/drain region and a second contact arranged over the first contact. A dielectric cap is formed over the second contact. A via is formed that extends in a vertical direction through the dielectric cap to the second contact. An interconnect is formed over the dielectric cap, and is connected by the via with the second contact.

Abstract: The vertical Hall element includes: a semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type; a first electrode set formed in a surface of the semiconductor layer and including a first drive current supply electrode, a Hall voltage output electrode, and a second drive current supply electrode aligned along a straight line extending in a first direction in this order; and second to fifth electrode sets each having the same configuration as the configuration of the first electrode set and aligned with the first electrode set along a straight line extending in a second direction perpendicular to the first direction. The Hall voltage output electrode has a first depth, the first and second drive current supply electrodes have a second depth that is larger than the first depth.

Abstract: A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.

Abstract: Provided is a low cost semiconductor device in which occurrence of chipping and a crack during dicing is suppressed. A nitride layer (silicon nitride layer) 23 is formed on an oxide layer 22. In FIG. 1, a thick organic layer 24 is formed as a top layer. The semiconductor device 1 is characterized by its structure on a side of its end portion. In FIG. 1, the end portion E of the semiconductor device 1 is formed by cutting with a blade in the vertical direction during dicing. An edge E1 of both the oxide layer 22 and the nitride layer is located apart from an edge of a semiconductor substrate 10. An edge E2 of the organic layer 24 on the nitride layer 23 is located inside the edge E1 of the nitride layer 23 (on a side more distant from the edge E).

Abstract: A transistor includes a semiconductor substrate having a first terminal and a gate region, and an interconnect structure formed of multiple layers of dielectric and electrically material on an upper surface of the semiconductor substrate. The electrically conductive material includes first and second layers, the second layer being spaced apart from the first layer by a first dielectric layer of the dielectric material, the first layer residing closest to the upper surface of the semiconductor substrate relative to the second layer. The interconnect structure includes a pillar formed from the conductive material. The pillar is in electrical contact with the first terminal, the pillar extends through the dielectric material, and the pillar includes a pillar segment in the first layer of the conductive material. The interconnect structure also includes a shield structure in the first layer of the conductive material and positioned between the pillar segment and the gate region.

Abstract: To improve the reliability of a semiconductor device. The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad formed on an uppermost wiring layer of the plurality of wiring layers, a surface protection film which includes an opening on the pad and is made of an inorganic insulating film, a rewiring formed on the surface protection film; a pad electrode formed on the rewiring, and a wire connected to the pad electrode. The rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion has a rectangular shape when seen in a plan view.

Abstract: An organic EL display device includes a bank having an inclined surface, a first electrode formed on the inclined surface, an organic film including a light emitting layer and directly contacting the first electrode on the inclined surface, and a second electrode directly contacting the organic film on the inclined surface.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is on the semiconductor substrate. A buried semiconductor layer of the second conductivity type is on the first semiconductor layer. A second semiconductor layer of the second conductivity type is on the buried semiconductor layer. A trench extends through each of the second semiconductor layer, the buried semiconductor layer, and the first semiconductor layer, and into the semiconductor substrate. An insulating structure lines walls of the trench. A conductive filling in the trench is electrically coupled to the semiconductor substrate at a bottom of the trench.

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a memory cell on a homogeneous bottom electrode via (BEVA) top surface. In some embodiments, the integrated circuit comprises a conductive wire, a via dielectric layer, a via, and a memory cell. The via dielectric layer overlies the conductive wire. The via extends through the via dielectric layer to the conductive wire, and has a first sidewall, a second sidewall, and a top surface. The first and second sidewalls of the via are respectively on opposite sides of the via, and directly contact sidewalls of the via dielectric layer. The top surface of the via is homogenous and substantially flat. Further, the top surface of the via extends laterally from the first sidewall of the via to the second sidewall of the via. The memory cell is directly on the top surface of the via.

Abstract: In order to improve reliability of a semiconductor device, the semiconductor device includes a semiconductor chip, a die pad, a plurality of leads, and a sealing portion. The die pad and the leads are made of a metal material mainly containing copper. A plating layer is formed on a top surface of the die pad. The plating layer is formed by a silver plating layer, a gold plating layer, or a platinum plating layer. The semiconductor chip is mounted on the plating layer on the top surface of the die pad via a bonding material. The plating layer is covered by the bonding material not to be in contact with the sealing portion.

Abstract: An integrated circuit device includes a substrate, first and second fin-type active areas which extend in a first direction on the substrate, first and second gate lines on the substrate that extend in a second direction that crosses the first direction, and first and second contact structures. The first and second gate lines intersect the first and second fin-type active areas, respectively. The first contact structure is on the first fin-type active area at a side of the first gate line and contacts the first gate line. The second contact structure is on the second fin-type active area at a side of the second gate line. The first contact structure includes a first lower contact including metal silicide and a first upper contact on the first lower contact. The second contact structure includes a second lower contact including metal silicide and a second upper contact on the second lower contact.

Abstract: A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.