Abstract: A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 ?) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

Abstract: An electronic device or signal processing device consists of a rectifier and capacitor which share common elements facilitating the construction and application of the device to various types of substrates and, particularly, flexible substrates. Components of the device may be fabricated from organic conductors and semiconductors.

Abstract: The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

Abstract: A semiconductor device capable of high speed operation with a substantially small interlayer capacitance is produced by steps of using an insulating film comprising an organic insulating film and an insulating film composed of an organometallic polymer material as an interlayer insulating film formed by coating, patterning the insulating film in a semi-thermosetting state, etching the organic insulating film as the lower layer by means of the organometallic polymer as a mask, using a plasma gas containing oxygen as the main component, and then conducting ultimate baking treatment of these insulating films.

Abstract: A ferro-electric memory device includes a first ferro-electric capacitor which is selectively formed on a first insulating film and has a first lower electrode, a first ferro-electric film, and a first upper electrode, a first hydrogen barrier film which has first to third portions, the first portion being formed on the first insulating film, the second portion covering the side surfaces of the first lower electrode, first ferro-electric film, and first upper electrode, and the third portion being formed on the upper surface of the first upper electrode, a first interlayer formed on the second portion, and a second hydrogen barrier film which has fourth to sixth portions, the fourth portion having a first contact portion which comes into contact with at least part of the first portion, the fifth portion being formed on the first interlayer, and the sixth portion being formed on the third portion.

Abstract: There are provided a power switching element including a first semiconductor layer of a first conductivity type; a plurality of second semiconductor layers of a second conductivity type, which are in a columnar shape, and arranged in the first semiconductor layer at certain intervals in a direction parallel to a layer surface of the first semiconductor layer; a first electrode formed on a surface of one side of the first semiconductor layer, the first electrode being electrically connected with the first semiconductor layer; a plurality of third semiconductor layers selectively formed in a surface region of the other side of the first semiconductor layer, the third semiconductor layers being connected to the second semiconductor layers; a fourth semiconductor layer of the first conductivity type selectively formed in a surface region of the third semiconductor layers; second electrodes formed so as to contact surfaces of the third semiconductor layers and the fourth semiconductor layer; and gate electrodes fo

Abstract: An electronic device includes: a circuit board, at least part of the circuit board being formed of two or more types of semiconductor chips having different functions, arranged so as not to overlap, and fixed to each other; and a plurality of operating elements formed over the circuit board.

Abstract: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum nitride barrier layer, on a substrate by using an atomic layer deposition process (a vapor deposition process that includes a plurality of deposition cycles) with a refractory metal precursor compound, an organic amine, and an optional silicon precursor compound.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: Metal oxide semiconductor transistors and devices with such transistors and methods of fabricating such transistors and devices are provided. Such transistors may have a silicon well region having a first surface and having spaced apart source and drain regions therein. A gate insulator is provided on the first surface of the silicon well region and disposed between the source and drain regions and a gate electrode is provided on the gate insulator. A region of insulating material is disposed between a first surface of the drain region and the silicon well region. The region of insulating material extends toward but not to the source region. A source electrode is provided that contacts the source region. A drain electrode contacts the drain region and the region of insulating material.

Abstract: A rectification chip terminal structure for soldering a rectification chip on a terminal filled with a packaging material to form a secured mounting for the rectification chip is to be inserted in a coupling bore of a circuit board. The structure includes a helical buffer portion, a spacer zone containing a space, a tapered section inclining towards the center of the terminal, a bend spot having latch rings to provide coupling, and a deck having a bulged ring. The structure can prevent bending and deformation under external forces, and form a stress buffer zone to prevent the chip from being damaged and moisture from entering. It can be installed easily in the coupling bore of the circuit board and hold the packaging material securely without breaking away.

Abstract: A semiconductor device comprising a laminate of plural insulating substrates 101 to 104 on which are mounted semiconductor chips (electronic parts) 12, wherein, when the lower-most insulating substrate is regarded to be a first insulating substrate 101 and other insulating substrates to be second insulating substrates 102 to 104 among the insulating substrates that are laminated; second electrically conducting wirings 112 to 114 are so provided as to protrude beyond the peripheral edges of the second insulating substrates and are folded toward the side of other surfaces of the second insulating substrates, and the thus folded second electrically conducting wirings are electrically connected to the electrically conducting wirings on the lower insulating substrates.

Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

Abstract: A semiconductor integrated circuit device includes a semiconductor region of a first conductivity type. A first insulated-gate field effect transistor having a source/drain region of a second conductivity type connected to an output terminal is formed on the semiconductor region. Further, a semiconductor region of a second conductivity type connected to the gate of the transistor is formed adjacent to the source/drain region of the transistor on the semiconductor region.

Abstract: An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.

Abstract: A semiconductor device comprises; a semiconductor substrate having a first region and a second region; a plurality of first sub-external terminals disposed on the first region; a plurality of second sub-external terminals composed of terminals to be grounded and terminals to be connected to a power source; a plurality of second external terminals disposed on the second region; a first sub-wiring structure provided on the first region for electrically connecting the plurality of first sub-external terminals and a plurality of circuit element connecting pads; a second sub-wiring structure for electrically connecting the plurality of second sub-external terminals and the plurality of circuit element connecting pads; and a plurality of second wiring structures provided from the first region to the second region for electrically connecting the plurality of second external terminals and the plurality of circuit element connecting pads.

Abstract: The present invention relates to a method of bonding a first member (110, 210, 130, 230, 410, 430, 510, 530, 610) to a second silicon member (120, 220, 420a, 420b, 600) through anodic bonding. The method comprises the steps of selectively depositing on said first member bondable sections (170a, 170b, 270, 470a, 470b, 470c, 570, 620) before bringing said first and second members together for anodic bonding.

Abstract: With a stopper layer 19 as an etching stopper, a second groove 14a and a contact hole 13a are formed. Copper is buried inside the second groove 14a and the contact hole 13a, thereby forming a plug layer 22 and an overlying wiring layer 21 connected to an underlying wiring layer 17 via the plug layer 22. The stopper layer 19 is comprised of Si, C and N as essential components. First and second cap layers 18 and 23 are also comprised of Si, C and N as essential components.

Abstract: An improved semiconductor device fabrication method comprises insertion of a semiconductor wafer into a high-pressure heated chamber and deposition of a low melting-point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.

Abstract: A semiconductor package includes a semiconductor chip connected to lead frames by wires and outer leads protruding from the semiconductor package. At this time, the outer leads are connected to the lead frames and grooves into which the outer leads are inserted into are provided in the semiconductor package, wherein the grooves are connected the lead frames. In mounting a first and a second semiconductor package, the outer leads of the first semiconductor package are inserted into the grooves of the second semiconductor package.