Abstract: A bipolar transistor structure for use in integrated circuits where the active device is processed on the sidewall of an n-hill so that the surface footprint does not depend on the desired area of active device region (emitter area). This structure, which is referred to as a Horizontal Current Bipolar Transistor (HCBT), consumes a smaller area of chip surface than conventional devices, thereby enabling higher packing density of devices and/or the reduction of integrated circuit die size. The device is fabricated with a single polysilicon layer, without an epitaxial process, without demanding trench isolation technology, and with reduced thermal budget. Fabrication requires fewer etching processes and thermal oxidations than in conventional devices.

Abstract: An object of the present invention is to increase adhesiveness between thin films, particularly a high molecular film formed on an insulating surface, and the present invention provides a semiconductor device with high reliability and a method for manufacturing the semiconductor device with high yield. A semiconductor device of the present invention comprises a laminate structure formed in close contact with an organic insulating film on a hydrophobic surface of an inorganic insulating film including silicon and nitrogen. A film having the hydrophobic surface is an insulating film having a contact angle of water of equal to or more than 30°, preferably of equal to or more than 40°.

Abstract: Provided is a high voltage transistor in a flash memory device comprising: a source/drain junction of a DDD structure consisting of a high-concentration impurity region and a low-concentration impurity region surrounding the high-concentration impurity region, the high-concentration impurity region being formed in parallel with a gate electrode at a distance spaced by a location in which a contact hole is formed, and having a rectangular shape whose width is the same as or wider than that of the contact hole and whose length is the same as or narrower than that of an active region through which the gate electrode passes. Accordingly, a current density to pass the gate electrode neighboring the contact hole portion and a current density to pass the gate electrode at a portion where the contact hole cannot be formed become uniform. A uniform and constant saturation current can be obtained regardless of the number of the contact hole.

Abstract: Semiconductor devices and methods to form a trench in a semiconductor device are disclosed. A disclosed process comprises: forming a hollow by etching a portion of a semiconductor substrate; forming a side wall layer in an inner side wall of the hollow; forming a trench by further etching the semiconductor substrate exposed through the bottom of the hollow; and filling the trench by forming an insulation film on the side wall layer and the trench.

Abstract: A chip scale packaging with improved heat dissipation capability is disclosed. A chip or die is adhered to the first surface of a packaging substrate having a plurality of metalized through holes thereon. A functional solder ball array is implanted on the second surface of the packaging substrate. Heat-dissipating solder balls are implanted around the functional solder ball array on the second surface of the packaging substrate. The heat-dissipating solder balls are connected to the metalized through holes. The bonding pads of the chip are bonded through a central window to the corresponding bonding pads on the second surface of the packaging substrate.

Abstract: A gate structure includes a gate dielectric layer disposed on a semiconductor substrate. A metal gate conductor is disposed on the gate dielectric layer. A cap layer is disposed on the metal gate conductor. At least one spacer covers sidewalls of the metal gate conductor and the cap layer, such that the cap layer and the spacer encloses the metal gate conductor layer therein. At least one self-aligned contact structure formed next to the metal gate conductor on the semiconductor substrate. As such, the cap layer and the spacer separate the self-aligned contact structure from directly contacting the metal gate conductor.

Abstract: A power transistor, formed from transistors connected in parallel, each transistor is formed in an active region using a relatively long gate called a gate finger that is typically formed from polysilicon that accumulates resistance over its length. To alleviate this, the gate finger is strapped to a metal line at tabs adjacent to the finger gate over the active area, typically over the source, but the tabs add gate-to-source capacitance. This was previously quite small but as gate dielectrics have gotten thinner there is more capacitive coupling to the substrate by the tabs, and as gates have gotten thinner there is more resistance in the polysilicon finger gates. Both have the effect of increasing the RC time constant of the gate finger. This increase in RC time constant is alleviated by increasing the thickness of the dielectric separating the tabs from the substrate thereby reducing the capacitance caused by the tabs.

Abstract: A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.

Abstract: A semiconductor device includes a semiconductor chip having an electrode pad electrically connected to an integrated circuit and a conducting part electrically connected to the electrode pad; an insulating material formed on a side of the semiconductor chip; and a conductive pattern to extend from a top of a front side of the insulating material to the conducting part of the semiconductor chip.

Abstract: In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Abstract: A data value is stored in a random access memory cell by driving the bit lines of the cell to complementary values representative of the value. The word line for the cell is driven to make a cell selection and cause the data value to be loaded into the cell from the bit lines. Thereafter, the word line is deselected. Following deselection, both bit lines are discharged to a logic low level. During discharging, however, a leakage current is allowed to flow through at least one of the bit lines so that the memory cell maintains the stored data value.

Abstract: An integrated circuit employable with a power converter. In one embodiment, the integrated circuit includes a transistor employable as a switch of a power train of the power converter including a gate located over a channel region recessed into a semiconductor substrate. The transistor also includes a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor further includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region. The integrated circuit also includes a driver switch of a driver configured to provide a drive signal to the transistor and formed on the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.

Abstract: A thin film transistor substrate manufacturing method, including the steps of forming on a first region of a transparent insulating substrate a first semiconductor film with a first film thickness that is crystallized through excimer laser irradiation; forming on a second region of the transparent insulating substrate a second semiconductor film that is laterally crystallized through continuous wave laser irradiation, the second semiconductor film being arranged to have a film thickness that is greater than or equal to the first film thickness; forming a first thin film transistor on the first semiconductor film; and forming on the second semiconductor film a second thin film transistor that operates at a speed greater than a speed of the first thin film transistor.

Abstract: Thinning and dicing substrates using inductively coupled plasma reactive ion etching (ICP RIE). When dicing, a hard photo-resist pattern or metal mask pattern that defines scribe lines is formed on a sapphire substrate or on a semiconductor epitaxial layer, beneficially by lithographic techniques. Then, the substrate is etched along the scribe lines to form etched channels. An etching gas comprised of BCl3 and/or BCl3/Cl2 gas is used (optionally, Ar can be added). Stress lines are then produced through the substrate along the etched channels. The substrate is then diced along the stress lines. When thinning, a surface of a substrate is subjected to inductively coupled plasma reactive ion etching (ICP RIE) using BCl3 and/or BCl3/Cl2 gas, possibly with some Ar. ICP RIE is particularly useful when working sapphire and other hard substrates.

Abstract: The present invention discloses a novel ferroelectric transistor design using a resistive oxide film in place of the gate dielectric. By replacing the gate dielectric with a resistive oxide film, and by optimizing the value of the film resistance, the bottom gate of the ferroelectric layer is electrically connected to the silicon substrate, eliminating the trapped charge effect and resulting in the improvement of the memory retention characteristics. The resistive oxide film is preferably a doped conductive oxide in which a conductive oxide is doped with an impurity species. The doped conductive oxide is most preferred to be In2O3 with the dopant species being hafnium oxide, zirconium oxide, lanthanum oxide, or aluminum oxide.

Abstract: Disclosed is a method of determining causes of intrinsic oscillations in a double-barrier quantum-well intrinsic oscillator comprising developing an emitter quantum-well (EQW) from a double-barrier quantum-well system (DBQWS); coupling the EQW to a main quantum-well (MQW), wherein the MQW is defined by double-barrier heterostructures of a resonant tunneling diode; using energy subband coupling to induce quantum-based fluctuations in the EQW; creating intrinsic oscillations in electron density and electron current in the DBQWS; forming a distinct subband structure based on the intrinsic oscillations; and identifying a THz-frequency signal source based on the quantum-based fluctuations, wherein the intrinsic oscillations comprise maximum subband coherence, partial subband coherence, and minimum subband coherence, wherein the energy subband is a quantum mechanical energy subband, wherein the intrinsic oscillations occur proximate to a bias voltage point in the range of 0.224 V and 0.

Abstract: A broad-spectrum Al(1-x-y)InyGaxN light emitting diode (LED), including: a substrate, a buffer layer, an N-type cladding layer, at least one quantum dot emitting layer, and a P-type cladding layer. The buffer layer is disposed over the substrate. The N-type cladding layer is disposed over the buffer layer to supply electrons. The quantum dot emitting layer is disposed over the N-type cladding layer and includes plural quantum dots. The dimensions and indium content of the quantum dots are manipulated to result in uneven distribution of character distribution of the quantum dots so as to increase the FWHM of the emission wavelength of the quantum dot emitting layer. The P-type cladding layer is disposed over the quantum dot emitting layer to supply holes. A broad-spectrum Al(1-x-y)InyGaxN yellow LED may thus be made from the LED structure of this invention, with an emission wavelength at maximum luminous intensity falling within a range of 530˜600 nm, and FWHM within a range of 20˜150 nm.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, an insulating region provided on the semiconductor substrate, a first capacitor provided above the insulating region, a second capacitor provided above the insulating region and adjacent to the first capacitor, a conductive hydrogen-barrier film which prevents diffusion of hydrogen into the first and second capacitors and connects a bottom electrode of the first capacitor with a bottom electrode of the second capacitor, the conductive hydrogen-barrier film having a first portion interposing between the insulating region and the first capacitor and between the insulating region and the second capacitor.

Abstract: Concerning an art related to a manufacturing method for a semiconductor device having an integrated circuit using thin film transistors on a substrate, a problem is to provide a condition for forming an amorphous silicon film having distortion. In the deposition of an amorphous silicon film using a sputter method, a condition is provided with a frequency of 15 to 25 kHz and a deposition power of 0.5 to 3 kW. This can sufficiently contain Ar at 10×1020/cm3 or more in an amorphous silicon film, thus making possible to form an amorphous silicon film having distortion.