Abstract: A transistor includes a substrate and a device isolation layer that is formed on the substrate to define an active region. A gate pattern crosses over the active region. A gate insulation layer is interposed between the gate pattern and the active region. Source and drain regions are formed in the active region adjacent to respective sides of the gate pattern. A channel region is disposed in the active region between the source and drain regions. The channel region includes a recessed portion.

Abstract: A system-on chip (SOC) (100) and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks (120, 220) and ESD protected pads (302, 304, 306, 308, 310, 312, and 314). A VDD isolation pad (302) is connected to an N well ring (124) of the first noise sensitive circuit (120) to collect noise from the substrate (110) and isolate the circuit from the P well region (112). A ground protected pad (304) is connected to an isolated P well (126) of a first noise sensitive circuit (120). The ground pad (304) collects noise from the isolated P well (126) and sends it to ground. A dedicated ground isolation pad (306) is connected to a P well ring (224) of a second noise sensitive circuit (220). The dedicated ground isolation pad (306) collects noise from the P well ring (224) and sends it to ground.

Abstract: A silicon germanium heterojunction bipolar transistor device and method comprises a semiconductor region, and a diffusion region in the semiconductor region, wherein the diffusion region is boron-doped, wherein the semiconductor region comprises a carbon dopant therein to minimize boron diffusion, and wherein a combination of an amount of the dopant, an amount of the boron, and a size of the semiconductor region are such that the diffusion region has a sheet resistance of less than approximately 4 Kohms/cm2. Also, the diffusion region is boron-doped at a concentration of 1×1020/cm3 to 1×1021/cm3. Additionally, the semiconductor region comprises 5–25% germanium and 0–3% carbon. By adding carbon to the semiconductor region, the device achieves an electrostatic discharge robustness, which further causes a tighter distribution of a power-to-failure of the device, and increases a critical thickness and reduces the thermal strain of the semiconductor region.

Abstract: A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to accurately define a resistance value of resistors. Subsequently, at least one insulating layer is coated on a surface of the circuit board having the patterned resistive material. At least one patterned second circuit layer is formed on the insulating layer and electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer or plated through holes formed through the circuit board.

Abstract: In a high-performance semiconductor integrated circuit, the standby current is reduced by preventing current leakage in a semiconductor integrated circuit device, for example, the memory cell of an SRAM. A gate electrode G is formed on semiconductor substrate 1 and n+-type semiconductor regions 17 (source/drain regions) are formed in the semiconductor substrate on both sides of this gate electrode. Within the same apparatus and under near-vacuum conditions, a depth of 2.5 nm or less is etched away from the surfaces of the source/drain regions and gate electrode, a film of Co is then formed on the source/drain regions, and thermal processing is applied to form CoSi2 layer 19a. As a result, current leakage in the memory cell can be prevented and this method can be applied to semiconductor integrated circuit devices that have low current consumption or are battery-driven.

Abstract: An insulating film with a linear concave portion is formed and a semiconductor film is formed thereon by deposition. The semiconductor film is irradiated with laser light to melt the semiconductor film and the melted semiconductor is poured into the concave portion, where it is crystallized. This makes distortion or stress accompanying crystallization concentrate on other regions than the concave portion. A surface of this crystalline semiconductor film is etched away, thereby forming in the concave portion a crystalline semiconductor film which is covered with side walls of the concave portion from the sides and which has no other grain boundaries than twin crystal. TFTs and memory TFTs having this crystalline semiconductor film as their channel regions are highly reliable, have high field effect mobility, and are less fluctuated in characteristic. Accordingly, a highly reliable semiconductor memory device which can operate at high speed is obtained.

Abstract: Provided are a composition for forming porous film which can form a porous film having practical mechanical strength in a simple and low cost process; a porous film and a method for forming the film; and an inexpensive, high-performing and highly reliable semiconductor device comprising the porous film inside. More specifically, provided is a composition for forming porous film, comprising a polymer which is obtainable by hydrolyzing and condensing one or more silane compounds represented by Formula (1), or preferably by hydrolyzing and co-condensing one or more silane compounds represented by Formula (1) and one more silane compounds represented by Formula (2), Formulas (1) and (2) being: (R1)aSi(R2)4-a ??(1) (R3)bSi(R4)4-b ??(2) Also provided is a method for forming porous film comprising a step of applying said composition on a substrate to form film and a step of transforming the film into porous film.

Abstract: A power transistor, formed from transistors connected in parallel, each transistor is formed in an active region using a relatively long gate called a gate finger that is typically formed from polysilicon that accumulates resistance over its length. To alleviate this, the gate finger is strapped to a metal line at tabs adjacent to the finger gate over the active area, typically over the source, but the tabs add gate-to-source capacitance. This was previously quite small but as gate dielectrics have gotten thinner there is more capacitive coupling to the substrate by the tabs, and as gates have gotten thinner there is more resistance in the polysilicon finger gates. Both have the effect of increasing the RC time constant of the gate finger. This increase in RC time constant is alleviated by increasing the thickness of the dielectric separating the tabs from the substrate thereby reducing the capacitance caused by the tabs.

Abstract: The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

Abstract: Integrated stacked microchannel heat exchanger and heat spreaders for cooling integrated circuit (IC) dies and packages and cooling systems employing the same are disclosed. In one embodiment, a stacked microchannel heat exchanger is operatively and thermally coupled to an IC die or package using an interstitial solder or a solderable material in combination with solder. In another embodiment, a stacked microchannel heat exchanger is operatively and thermally coupled to an IC die or package using an adhesive. In a further embodiment, a stacked microchannel heat exchanger is operatively coupled to an IC die or package by fasteners and is thermally coupled to the IC die or package using a thermal interface material. The integrated stacked microchannel heat exchanger and heat spreaders may be employed in a closed loop cooling system including a pump and a heat rejecter.

Abstract: A pixel including a substrate of a first conductivity type, a photodetector of a second conductivity type that is opposite the first conductivity type and configured to convert incident light to a charge, a floating diffusion of the second conductivity, and a transfer region between the photodetector and floating diffusion. A gate is formed above the transfer region and partially overlaps the photodetector and is configured to transfer charge from the photodetector to the floating diffusion. A pinning layer of the first conductivity type extends at least across the photodetector from the gate. A channel region of the first conductivity type extends generally from a midpoint of the gate at least across the photodiode and is formed by an implant of a dopant of the first conductivity and having a concentration such that a dopant concentration of the transfer region is greater proximate to the photodetector than proximate to the floating diffusion.

Abstract: The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segments of dielectric material, with the thin and thicker segments of dielectric material being within an opening. A gateline material is formed within the opening and over the thin and thicker segments of dielectric material. The construction comprising the gateline material over the thin and thicker segments of dielectric material can be supported by a semiconductor substrate having a primary surface which defines a horizontal direction. The thin and thicker segments of dielectric material can comprise upper surfaces substantially parallel to the primary surface of the substrate, and can join to one another at steps having primary surfaces substantially orthogonal to the primary surface of the substrate.

Abstract: A method of realizing an active matrix display device having flexibility is provided. Further, a method for reducing parasitic capacitance between wirings formed on different layers is provided. After fixing a second substrate to a thin film device formed on a first substrate by bonding, the first substrate is removed, and wirings and the like are formed in the thin film device. The second substrate is removed next, and an active matrix display device having flexibility is formed. Further, parasitic capacitance can be reduced by forming wirings, after removing the first substrate, on the side in which a gate electrode over an active layer is not formed.

Abstract: A semiconductor structure with device trench and a semiconductor device in the device trench, that enables realization of high integration, lowered on-resistance, reduction in switching losses and a high operation speed in a semiconductor device provided with a lateral IGBT, and that prevents malfunctions such as latchup when IGBTs or an IGBT and CMOS devices are integrated together. The structure includes an SOI substrate having a supporting substrate, an oxide film and a p?-semiconductor layer. An island-like element-forming region is isolated by a trench isolation region from surroundings. The trench isolation region includes an isolation trench with an insulation film on its inner wall. The device trench is formed in the element-forming region. A gate electrode is formed with a gate insulator film in the device trench. A collector region and an emitter region outside are provided respectively on the bottom and the outside of the device trench.

Abstract: A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.

Abstract: A semiconductor device may include a borderless logic array and area I/Os. The logic array may comprise a repeating core, and at least one of the area I/Os may be a configurable I/O. Furthermore, the configurable I/O may comprise at least one metal layer that is the same for all I/O configurations.

Abstract: A dielectric layer may be formed by depositing the dielectric layer to an intermediate thickness and applying a nitridation process to the dielectric layer of intermediate thickness. The dielectric layer may then be deposited to the final, desired thickness.

Abstract: A semiconductor device has a first substrate and a second substrate. The first substrate has first electrodes on at least one surface. The second substrate has concave portions on a surface, and second electrodes provided on bottom surfaces of the concave portions. The semiconductor device further has metallic members located between the first electrodes of the first substrate and the second electrodes of the second substrate. The metallic members have a height greater than a depth of the concave portions of the second substrate, and electrically and mechanically bond the first electrodes of the first substrate and the second electrodes of the second substrate.

Abstract: The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a drain-extended well (115) having a curved region (125) and a straight region (130) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The transistor (100) further includes a centered source/drain (120) surrounded by the drain-extended well (115) and separated from an outer perimeter (135) of the drain-extended well (115). A separation in the curved region (145) is greater than a separation in the straight region (150). Other embodiments of the present invention include an integrated circuit (300) and a method of manufacturing a transistor (200).

Abstract: A barrier implanted region of a first conductivity type located below an isolation region of a pixel sensor cell and spaced from a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The barrier implanted region is formed by conducting a plurality of deep implants at different energies and doping levels below the isolation region. The deep implants reduce surface leakage and dark current and increase the capacitance of the photodiode by acting as a reflective barrier to electrons generated by light in the doped region of the second conductivity type of the photodiode.