Abstract: A transmission line sampling circuit for a T1 line is disclosed. A multi phase oscillator is connected to a plurality of state machines which are connected in parallel to a transmission line. The use of a plurality of state machines to sample the transmission line effectively increases the sample rate of the transmission line beyond that which can ordinarily be supported by a single phase oscillator running at the same frequency of the multi phase oscillator. The outputs of the plurality of state machines are provided to an arbitrator and to a MUX wherein the arbitrator decides which of the four state machines outputs should be switched through the MUX and produced transmitted on an output line.

Abstract: A large-area electronic device comprises an array (1) of device elements (2,3) coupled to row and column conductors (A and B). The column conductors (B) are arranged in groups, (e.g M, M+1, M+2), and a column multiplexer circuit (C) couples the column conductors (B) of a respective group to a respective common terminal (5). The present invention provides a compatible multiplexer circuit (C) for the array (1), the operation of the circuit (C) using electrical switching rather than optical switching. This multiplexer circuit (C) for each column conductor comprises a diode bridge (SD3 to SD6) and may include a clamping switch (SD1, SD2). A signal is transmitted between the column conductor (B) and a common output terminal (5) in a first state of the diode bridge (SD3 to SD6). The potential of the column conductor (B) is clamped by the clamping switch (SD1, SD2) in a second state of the diode bridge.

Abstract: An automatic microscope comprises an operating member operated electrically, and a detector for outputting an operation signal upon detecting the presence of an observer of the microscope in a predetermined range around the microscope, thereby operating the operating member. The operating member may be a shutter for opening and closing an optical path of the optical system of the microscope, an optical path switching member for switching the optical path of the optical system, a main power switch of the microscope, an auxiliary power switch of the microscope or a power switch for an illuminating light source, and the detector may be a light reflection detector including a light source and a photosensor unit for receiving the reflected light of the light emitted from the light source.

Abstract: An arrangement for monitoring an alternating signal with respect to its state as mark-to-space ratio or direct-current component, in which the alternating signal is modified so that its mark-to-space ratio or direct-current component can be detected by simple comparison with reference signals. Various information is then transmitted over a line, and the operation of the stage that generates the alternating signal can also be monitored.

Abstract: A voltage detector circuit for instantaneously detecting abnormal voltages in a micro controller includes a voltage detection circuit connected between the power supply and reset voltage ends of an internal circuit of the micro controller so as to instantaneously detect changes in the power supply, without the time delay associated with the external low pass filter that supplies the reset voltage. The detecting circuit is a logic "NOT" gate which has a power supply connecting end connected to a reset voltage end of the internal circuit, an input end connected to the power supply end of the internal circuit, and an output end connected to a cooperating input end of the latch circuit, so that the latch circuit latches a signal output by the voltage detector whenever an abnormal power supply voltage is detected, and outputs a flag signal to the micro controller to effect an instantaneous reset of the micro controller.

Abstract: To reduce drift in a sampling clock for framed data, a phase detector senses the time difference between (i) the time when a reference mark for the framed data is received and (ii) the time when the nominal number of oversampling clock cycles between reference timing marks is received. This difference is output to a clock controller which chooses a phase change rate based thereon. This phase change rate is applied to an oversampling clock to continuously, progressively, change the phase of the oversampling clock in a sense which tends to reduce this phase error. The phase changing clock is divided down by a frequency divider to generate a sampling clock. The phase of the oversampling clock is changed by generating multiple, equally spaced, phases of the oversampling clock and progressively changing the selection of the active phase.

Abstract: A clock signal generator comprises a phase locked loop circuit and a voltage level converting circuit. The phase locked loop circuit is supplied with a control base clock signal and an input clock signal which has a first frequency. The phase locked loop circuit converts the input clock signal to generate a PLL output clock signal which has the second frequency. The input clock signal has one of binary values that has a voltage level which is similar to a reference voltage level of a reference voltage. The voltage level converting circuit is supplied with the PLL output clock signal, the control base clock signal, the reference voltage, and a voltage level control signal. The voltage level converting circuit converts, in response to the control base clock signal, the reference voltage, and the voltage level control signal, the PLL output clock signal to generate an output clock signal which has an output voltage level which is different from the reference voltage level.

Abstract: The frequency multiplier 10 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

Abstract: A pulse-width modulator is disclosed which can be used, for example, in a power factor corrected electronic ballast circuit. The pulse-width modulator circuit combines a reference waveform signal with a second signal to form a composite waveform signal. The composite waveform signal is then compared with a reference voltage. The level of the pulse-width modulator's output depends upon the results of the comparison, such that a change in the level of the second signal causes an adjustment in the duty cycle of the output. In an electronic ballast application, the reference waveform can be a scaled version of the oscillator waveform found in the ballast's inverter circuit.

Abstract: An integrated circuit includes a plurality of MOSFETs on a substrate. A plurality of sensing MOSFETs are used to generate a plurality of comparison signals based upon comparing signals related to the sensed initial threshold voltages to respective reference voltages from a spread of high to low reference voltage values. The MOSFETs are biased to have a desired effective threshold voltage based upon the plurality of comparison signals. Logic decoding circuits accept the plurality of comparison signals and generate at least one bias control signal. Bias circuits are responsive to the at least one bias control signal for generating a desired bias voltage from among a plurality of bias voltages having a spread of high to low bias voltage values to thereby bias the plurality of MOSFETs to the desired effective threshold voltage. Method aspects of the invention are also disclosed.

Abstract: An "H" type amplifier circuit uses at least two current mirrors for alternately feeding current into the load in one direction and the other direction. In order to accelerate the turn-on of the current mirrors, a capacitance is associated with each of the two current mirrors. Each capacitance is alternately coupled in parallel with the input of its associated current mirror when this current mirror delivers current, and is coupled to the supply voltage terminals when this current mirror delivers no current. The operation is effected by means of a set of switches.

Abstract: A design method for an asynchronous sequential circuit that employs synchronous design techniques wherein a synchronous sequential circuit is designed to perform a desired function. A terminating state for the synchronous sequential circuit is then defined wherein the terminating state occurs before a transition to an idle state in the synchronous sequential circuit. A circuit is provided for latching at least one asynchronous input for the asynchronous sequential circuit and a circuit is provided for generating a synchronous clock that drives the synchronous sequential circuit such that the synchronous clock is enabled by a latched asynchronous input and is disabled by the terminating state of the synchronous sequential circuit.

Abstract: A method and system are provided. A clock signal is input and output at first and second nodes of integrated circuitry. The first node is connected through a selected one of a plurality of metallization paths of the integrated circuitry to the second node. Each of the metallization paths is connectable between the first and second nodes for delaying the clock signal by a respective amount of time between the first and second nodes, so that the clock signal at the second node is always delayed relative to the first node by the respective amount of time of the selected metallization path.

Abstract: A decoupling capacitor for an integrated circuit is operatively coupled to a supply and to control circuitry for isolating the capacitor. The control circuitry automatically isolates the capacitor in response to a current through the capacitor exceeding a certain threshold, but tends to restore the capacitor to operation if the current is merely caused by momentary conditions, rather than substantial failure of the capacitor. The control circuitry includes a first control device for automatically switching to an off state to isolate the capacitor in response to a voltage produced by the current exceeding a certain threshold. A discharging device tends to discharge the voltage and automatically turn on the first device when the current is caused by momentary conditions. The discharging device may include a control device responsive to an external control signal for switching the first control device on and off.

Abstract: A dynamic latching arrangement with a conditional driver, a system, and a method reduce power consumption, increase operating speed, and reduce the number of discrete components. The conditional driver selectively impresses a signal on an internal node of the circuit such that when a control signal is asserted, a signal related to the clock signal is generated, but when the control signal is not asserted, a different signal related to the clock signal is generated.

Abstract: Jitter is controlled in a phase locked loop (PLL) adaptively and continuously in real time by a jitter control circuit. The jitter control circuit makes periodic PLL output jitter measurements and causes sequential measurements to be compared. The comparison provides an indication as to whether output jitter is being improved or degraded. Charge pump gains associated with internal parameters and external parameters that adversely affect output jitter are modified in response to the comparisons. If output jitter is adversely affected by an increment or decrement of one of the gain values, then the gain value is moved in the opposite direction. Output jitter is optimized for both gain values. Such optimization occurs during normal circuit operation and is continuous so as to adapt to changing conditions.

Abstract: A circuit source has bias and modulation current generators for both p-type and n-type optical sources, and a pair of sources of control voltages for the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. An external signal allows selecting, by means of a control logic and CMOS gates, the generators required by the source. The circuit is made by using three pads of an integrated circuit, one for each control voltage source and the third comprising the current generators, the CMOS gates and the control logic.

Abstract: An on-chip clock waveform generator for generating from an externally supplied clock (EFI) an on-chip (internal) clock with a 50% duty cycle having a clock rate of 1/2, 1, or 2 times that of EFI, is based on a tapped delay line with a tap-to-tap differential delay of approximately 1% of the external clock (EFI) period. The waveform generator detects the tap at which a full period of delay occurs between delay line input and the tap. By knowing the tap for a first full period delay the generator determines the taps at which the 1/4, 1/2, and 3/4 period waveform states can be observed. The pulses corresponding to fractional periods, are used to generate standard pulse width streams that correspond to 1/4 period intervals. A programmed multiplexer/selector selects the proper sequence from these pulse streams to drive an RS flip-flop in order to produce the output 50% duty-cycle clock running at 1/2, 1, or 2 times the external (EFI) clock.

Abstract: A method for asserting signals onto an output line connected to a passive external pull-up resistor by using a fast edge rate signal driver is provided. The fast edge rate signal driver has first, second and third pull-down predrivers, first, second and third pull-up predrivers, first and second delay elements, and first, second and third output devices, and a PMOS and an NMOS current controller, and each of the output devices has one output terminal coupled to each other forming the output line.

Abstract: In a switching circuit, low insertion loss and enough isolation can be ensured at a desired frequency at the same time. An inductor is externally connected in parallel with the path between the drain and source of each of field-effect transistors built in a switching integrated circuit, and the inductor and the OFF capacitance of the field-effect transistor are made to generate parallel resonance. At this time, by suitably adjusting the inductance, low insertion loss and enough isolation are ensured at a desired frequency at the same time.