Abstract: A high speed capture latch includes differential data inputs, a latch clock input, a boost clock input, a current steering circuit, a switched current source, a latch element and first and second boost current sources. The current steering circuit has first and second differential control terminals which are coupled to the differential data inputs and control current through first and second current paths, respectively. The switched current source is coupled between the current steering circuit and a first voltage supply terminal and has a control terminal coupled to the latch clock input. The latch element is coupled between a second voltage supply terminal and the current steering circuit and provides a latch output. The first boost current source is coupled to the first current path between the latch element and the current steering circuit and has a control terminal coupled to the boost clock input.

Abstract: A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

Abstract: A substrate voltage detecting circuit includes a detection node, a transistor responsive to a detected substrate voltage for changing a comparison voltage, a differential amplifier for comparing the comparison voltage with a prescribed reference voltage and outputting an enable signal when the comparison voltage exceeds the reference voltage, and a transistor turned on in response to the enable signal for fixing the reference voltage at an L level. The internal voltage detecting circuit further includes transistors for reducing current consumption. Consequently, the responsibility thereof is improved even with small power consumption.

Abstract: A device for providing a balanced input over a photoelectric cell used in a motion picture film projector and for providing an unbalanced output audio signal for driving subsequent elements in an audio reproduction unit connected to the motion picture film projector, wherein the reproduced output audio signal has an improved quality over that of a previously known transformer output signal. The circuit supplies an unbalanced voltage signal in response to a current generated by a photoelectric cell having at least a first and second terminal. The circuit includes: a current to voltage converter for receiving the current from the first terminal of the photoelectric cell and providing a first output voltage and a current return unit connected to the current to voltage converter for receiving the first output voltage and for providing a second output voltage and for providing a return current along the second terminal of the photoelectric cell.

Abstract: A first signal .phi.1 is produced from an external clock CLK. A second ond signal .phi.2 is produced from a clock enabling signal CKE for controlling an internal clock of a SDRAM. A phase compensated signal .phi.3 is produced by advancing the phase angle of the signal .phi.1. A control signal .phi.4 is produced by a D-type flipflop from the signals .phi.1 and .phi.2. A phase-advanced internal clock .phi.6 is produced from the signals .phi.3 and .phi.4 through an RS-type flipflop and an OR gate. The phase-advanced internal clock .phi.6 thus has no error producing waveform.

Abstract: An integrated circuit driver for providing data to a communications channel comprises first and second output buffers coupled to first and second output conductors (e.g. bondpads) respectively. Each output buffer comprises a multiplicity of pull-up transistors and a multiplicity of pull-down transistors coupled to the associated output conductor through pull-up resistors and pull-down resistors, respectively. A multiplicity of delay circuits coupled to a data input node supply delayed data signals to the control terminals of the pull-up and pull-down transistors. Control circuitry is included for selectively activating the delay circuits. In a typical case, the control circuitry comprises multiplexers each having an output that is coupled to the input of a corresponding delay circuit. Advantages of the technique include a constant output impedance and waveshaping of the data output for reduction of harmonics.

Abstract: A dynamic/static signal converting circuit and method for use in a lamp driving device has a clock delay unit for delaying a system clock signal for a predetermined period of time; a converting unit for receiving a dynamic signal for driving an LED, synchronizing the dynamic signal with a delayed system clock signal and then converting the dynamic signal into a static signal; and an LED driving unit for driving the LED in response to the static signal output from the converting unit.

Abstract: A buffer which provides compensation for the RC time delay introduced by a switch matrix of a high density programmable logic device (PLD). The buffer includes circuitry to provide an input threshold which varies to compensate for the RC delay of the switch matrix on a high to low input signal transition. The buffer further includes a negative hysteresis circuit to prevent oscillations on slow rate low to high input signal transitions.

Abstract: In an integrated circuit, a central reference generator (3) generates a setpoint signal determining the operating characteristic required to be common to some of the functional components of the circuit. Lines (4-1 to 4-n) distribute this signal among units of the circuit, each unit comprising a functional Component (2-n). In each unit, a local adjustment circuit (5-n) receives the setpoint signal and generates an adjustment value. Correction circuitry adjusts the operating characteristic of a device in the local adjustment circuit (5-n) as a function of the adjustment value. The device is placed in proximity to the functional component and configured in such a way that the operating characteristic which is thus imposed on the device is also imposed on this component.

Abstract: A phase frequency detecting circuit is designed to produce an output voltage which varies with respect to an input phase difference between a base phase and a reference phase. Herein, a first phase frequency comparator produces a first phase error signal which is proportional to the input phase difference. A first integration circuit performs integration on the first phase error signal to produce a control voltage. Next, a second phase frequency comparator receives a frequency-divided base phase and a frequency-divided reference phase to produce a second phase error signal. A second integration circuit performs integration on the second phase error signal to produce a frequency-divided control voltage. An offset voltage creating circuit creates an offset voltage. Herein, the offset voltage is created based on the frequency-divided control voltage; and a sign thereof is determined responsive to a relationship between the control voltage and frequency-divided control voltage.

Abstract: A method and circuit spreads the narrow band emitted EMI of a clock signal. A first, high frequency, clock signal is received, for example, from an oscillator. The first clock signal is modulated, to produce a second clock signal, by inverting the first clock signal x times per L transitions of the first clock signal, where x and L are integers and x<L. Each inversion removes one transition of the first clock signal. The modulated clock signal has reduced EMI spectral density and may be utilized as a microprocessor high frequency master clock signal. Significantly, the modulated clock signal is synchronous with the first clock so that other circuitry which synchronizes to the modulated clock signal is also synchronized to the first clock signal clock. If needed by a particular system (e.g.

Abstract: A semiconductor integrated circuit device is intended to prevent generation of an unnecessary leak current and hence to reduce power consumption.

Abstract: A frequency multiplication circuit (10) includes a periodic interval selector (12) and a delay element (28) to produce an output signal (26) in phase with, and at a frequency multiple of a reference signal (18). During a first time interval, the periodic interval selector (12) bases the output signal (26) on the reference signal (18). During a second time interval, the periodic interval selector (12) bases the output signal (26) on a delayed signal (22) produced by the delay element (14) based upon the output signal (26). Feedback from the output of the periodic interval selector (12) through the delay element (14) and the operation of the periodic interval selector (12) causes the output signal (26) to be in phase with, and at a frequency multiple of the reference signal (18). Delay adjuster (52) adjusts delay produced by the delay element (14) to adjust the output signal (26) to cause the output signal (26) to have a desired duty cycle consistency.

Abstract: An integrated circuit memory comprises a circuit that keeps the column voltage constant during the recording of a binary value. This circuit has a differential amplifier which measures the difference between a reference voltage given by a voltage divider and a voltage representative of the bit line. This amplifier gives a signal that is applied to the gate of a transistor of the column-addressing circuit.

Abstract: A controllable one-shot circuit for use in a control unit of a memory circuit, for asserting a control signal with variable (and controllable) duration in response to a trigger signal, and a state machine for controlling memory operations of a memory circuit which includes such a controllable one-shot circuit. In preferred embodiments, the one-shot and the state machine of which it is a part are implemented as parts of a single memory chip (preferably, a nonvolatile memory chip such as an integrated flash memory circuit). Other aspects of the invention are methods of operating a state machine of a memory circuit to generate control signals for use in controlling memory operations performed by the memory circuit.

Abstract: An integrated circuit includes a data terminal, a supply potential terminal, a configuration signal generator with an input, a buffer circuit with a terminal and a bond pad connected to the input and the terminal. The bond pad is connected to the data terminal for operating the integrated circuit using the buffer circuit and the bond pad is connected to the supply potential terminal for operating the integrated circuit using the configuration signal generator. A method for producing such an integrated circuit includes connecting the input of the configuration signal generator and the terminal of the buffer circuit to the bond pad. The bond pad is connected to the supply potential terminal for operating the finished integrated circuit using the configuration signal generator, or to the data terminal for operating the finished integrated circuit using the buffer circuit.

Abstract: A single-phase clocking scheme for use in a VLSI chip having a plurality of localized logic blocks implemented thereon is presented. The present invention includes a first level global clock buffer for receiving an external global clock and producing a first level global clock. A plurality of second level clock buffers, one corresponding to each localized logic block, receive the first level global clock via protected equal length lines, and each produce a respective second level global clock. Each of the localized logic blocks include a plurality of third level clock buffers, wherein each third level clock buffer receives the second level global clock of its respective localized logic block, and each produces a third level local clock. The third level local clock buffers within each localized logic block generate different clocking schemes from each of the other third level local clock buffers contained within the same localized block.

Abstract: A source synchronous computer system to ensure the capturing of signals transmitted from a first component to a second component. An integrated circuit operating on a core clock signal and an I/O clock signal, the integrated circuit comprising a plurality of data drivers and a plurality of external I/O clock generators, wherein the external I/O clock generators generate external I/O clocks signals using circuitry identical to the data drivers except for a slight increase in the channel length of the pre-driver and driver transistors. These transistors control the transition time of the external I/O clock output node. By outputting data signals in the I/O clock domain and using the external I/O clock signals to synchronize transmission with external components, the integrated circuit ensures that the data signals transition before the transitions of the external I/O clock signals regardless of process induced signal variations.

Abstract: An RF IC having an improved transconductance comprises a first active device of a first conductance type having a gate, a drain and a source and a second active device of a second conductance type having a gate, a drain and a source. The second active device is coupled in series with the first active device. The gate of the first active device is coupled to the gate of the second active device. A current reuse circuit is coupled to the first active device and the second active device wherein a current flowing from the drain of the first active device is reused in the second active device. Whereby transconductance is increased without an increased current utilization and without an increase in noise.

Abstract: An oscillation stop signal holding latch 3 which stores a value deciding significant/unsignificant of an oscillation stop signal 4, and a NOR gate 21 which controls, when the oscillation stop signal 4 is significant, to stop the generation of a clock signal 7 and controls, when a predetermined signal is inputted from an input terminal 1 of an external signal in the abovementioned states with the oscillation stop signal being unsignificant, to resume the generation of the clock signal 7, and further a sampling circuit 10 between the input terminal 1 of the external signal and the oscillation stop signal holding latch 3 are provided. And a gate circuit 30 which forcibly makes the oscillation stop signal 4 become unsignificant so as to generate the clock signal 7 when the input signal from the input terminal 1 of the external signal is significant is provided. This enables the sampling circuit 10 to sample the input signal from the input terminal 1 of the external signal.