Abstract: A transmission line sampling circuit for a T1 line is disclosed. A multi phase oscillator is connected to a plurality of state machines which are connected in parallel to a transmission line. The use of a plurality of state machines to sample the transmission line effectively increases the sample rate of the transmission line beyond that which can ordinarily be supported by a single phase oscillator running at the same frequency of the multi phase oscillator. The outputs of the plurality of state machines are provided to an arbitrator and to a MUX wherein the arbitrator decides which of the four state machines outputs should be switched through the MUX and produced transmitted on an output line.

Abstract: An integratable transformer circuit for converting an asymmetrical input signal into a pair of symmetrical output signal currents and requiring only one IC connection pin. The circuit exhibits a low input impedance combined with good noise, gain and intermodulation performance up to high frequencies. The asymmetrical input terminal of the circuit is coupled to a node commonly coupled to the emitter of a common base transistor and to the base of a common emitter transistor. The common base transistor acts as a non-inverting current follower, the common emitter transistor as an inverting transimpedance amplifier. An input signal current is transferred to a first symmetrical output terminal via the node and the common base transistor, thereby producing a signal voltage at the node. This signal voltage modulates the collector current of the common emitter transistor, which is in phase opposition to the input signal current and is transferred to the second output terminal.

Abstract: A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section and a slave section, is disclosed and claimed. The master section includes a master latch structure, a master coupling circuit which connects the master latch structure to one of two supply voltages, and an input coupling circuit for applying data to the flip-flop. The slave section includes a slave latch structure directly interposed between two supply voltages, and a slave coupling circuit which connects the slave latch structure to the master latch structure. The number of transistors required to realize the D flip-flop circuit implementation of the invention is minimized by enlarging the source areas of transistors in the input coupling circuit, which results in a large stray capacitance and insures optimum operation of the master latch. In addition, transistors in the slave latch structure have non-minimal gate lengths.

Abstract: A flip-flop circuit able to commute in correspondence with any logic transition of the input signal using a flip-flop and a logic gate of the EXNOR type receiving at its input a signal and the inverted output of the flip-flop. To the output of the EXNOR gate is connected a set-reset flip-flop which allows a reset to be effected after each commutation of the circuit in order to prepare it for the next transition.

Abstract: A level shift circuit shifting logic levels of an SCFL circuit to logic levels of a DCFL circuit, including an SCFL circuit having complementary outputs; two source follower circuits with their inputs respectively connected to the complementary outputs of the SCFL circuit; a high/low detecting circuit detecting "high" or "low" signals which have DCFL levels from the two source follower circuits and outputting signals having logic levels according to the detection results; and DCFL circuits with inputs connected to outputs of the high/low detecting circuit. Therefore, it is possible to obtain a level shift circuit operating with a wider voltage range and in a wider temperature range than the prior art circuit.

Abstract: The digital phase detector detects a phase shift between a comparison clock pulse signal (VT) and a reference clock pulse signal (RT). It includes logic gates (STO,STA) for generating start and stop pulses from respective successive pulses of the comparison and reference clock pulse signals (RT,VT). A counter (ZG,Z) counts the pulses of a counter clock pulse signal (ZT) of a higher frequency in a time window between the start signal and the subsequent stop signal. The counter value of the counter is a measure of the phase shift between the comparison and reference clock pulse signals (VT,RT). Quantization errors in the phase shift signal are considerably reduced by providing a logical gate (VZ) for determining the sign of the phase shift and a device (.mu.P) for adding a constant, advantageously 0.5, to the counter value.

Abstract: Clock signal generating circuit for preventing occurrence of clock skew, totally preventing through current, and readily controlling the clock, which includes a master clock signal generating circuit 2M and a slave clock signal generating circuit 2S. The master clock signal generating circuit 2M generates a master clock signal MCLK at a high level based on a slave clock signal SCLK at a low level and a clock signal CLK at a low level, and generates a master clock signal MCLK at a low level based on the clock signal CLK at a high level. The slave clock signal generating circuit 2S generates a slave clock signal SCLK at a low level based on the clock signal CLK at a low level and a slave clock signal SCLK at a high level based on the master clock signal MCLK being at a low level and the clock signal CLK at a high level.

Abstract: A field-effect-controllable power semiconductor component has a drain terminal, a source terminal, a gate terminal, a drain-to-source voltage and a load current. A circuit configuration for detecting the load current of the power semiconductor component includes a further field-effect-controllable semiconductor component through which a fraction of the load current flows. The further semiconductor component has a drain terminal connected to the drain terminal of the power semiconductor component, a gate terminal connected to the gate terminal of the power semiconductor component, a source terminal and a drain-to-source voltage. A resistor at which a voltage proportional to the load current can be picked up, is connected to a fixed potential terminal. A controllable resistor is connected between the resistor and the source terminal of the further semiconductor component.

Abstract: A detect circuit receives a write enable signal, a column address strobe signal and an output control signal to predetect a mode in which data is input from an input/output terminal. While a substrate potential generation circuit normally operates, a substrate potential holding circuit also operates when the detect circuit detects the mode in which data is input, so that biasing capability of a substrate potential generating portion is increased before the data is actually input from the input/output terminal.

Abstract: A circuit, for incorporation into an electrical system, for providing a clock signal frequency to other circuitry such as a microprocessor and/or co-processor circuitry. The clock signal frequency varies its speed depending on the available voltage and current from a host power source. The circuit maximizes clock frequency by lowering the available voltage and increasing the available supply current. The circuit can therefore provide a higher clock speed and more current for switching transistors.

Abstract: According to the present invention, to drive a magnetron, a pulse voltage is applied to the gate electrode of a field effect transistor to make the field effect transistor conductive, so that a voltage stored in a storage condenser is discharged through the primary winding of a pulse transformer and the drain electrode-the source electrode of the field effect transistor. This discharge causes the voltage generated at the primary winding of the pulse transformer to be induced at the secondary winding of the pulse transformer. Thus, the magnetron connected to the secondary winding of the pulse transformer is driven.

Abstract: The cutoff process of a collector current of an insulated gate transistor is divided into an emitter-to-collector voltage recovery period and a collector current cutoff period. During the emitter-to-collector voltage recovery period the resistance of a gate resistor of the transistor is reduced, and during the collector current cutoff period the resistance of the gate resistor is increased. With this arrangement, the cutoff time is shortened, thereby reducing switching loss and suppressing surge voltage.

Abstract: A method and apparatus are provided for generating a ratioed clock signal. A first clock signal having a first frequency is output. At least one gating signal indicating ratio is output. In response to the first clock signal and the gating signal, a second clock signal is output. The second clock signal has a frequency that is substantially related to the first frequency by the ratio.

Abstract: A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a "buffer" and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.

Abstract: The present invention relates to a circuit that pulls down the power supply line in an electronic system to a low state when the electronic system is turned off. More specifically, the present invention is an active circuit that establishes a low impedance between a power supply line and a return line when a system's power is turned off, and establishes a high impedance between a power supply line and a return line when the system is turned on.

Abstract: A current generator stage for integrated analog circuits includes a current source connected between a supply voltage and a ground terminal. A current mirror is operationally connected to the current source to generate an output current. A bias circuit is operationally connected to the current source to perform switching of the current source from a first operating mode to a second operating mode. The bias circuit includes an energy storage circuit which, in a first circuit configuration, supplies to the current source a first predetermined voltage when the current source is in the first operating mode. The energy storage circuit in a second circuit configuration is a combination of first and second reactances to supply to the current source a second predetermined voltage when the current source is in the second operating mode.

Abstract: A test mode circuit for an integrated circuit includes a high voltage detector having an input for receiving a high voltage signal, a Schmitt trigger having an input coupled to the output of the high voltage detector, a latch having an input coupled to the output of the Schmitt trigger and an output for providing a test mode signal in a test operational mode, and additional control circuitry for disabling the high voltage detector and Schmitt trigger so that substantially all of the active current flow in the high voltage detector and Schmitt trigger is eliminated in a normal operational mode. The test mode circuit further includes circuitry for preventing a reset condition in the latch during the test mode until a power-down condition occurs. A glitch filter is also included, which is interposed between the output of the Schmitt trigger and the input to the latch.

Abstract: A multiplier presenting four multiplying branches, each formed by a buffer transistor and by two input transistors arranged in series to one another and connected between two output nodes and a common node. A biasing branch presents a diode-connected forcing transistor with its gate terminal connected to the gate terminal of all the buffer transistors, and its source terminal connected to the common node. The forcing transistor forces the input transistors to operate in the triode (linear) region, i.e., as voltage-controlled resistors, so that they conduct a current linearly proportional to the voltage drop between the respective source and gate terminals, and the currents through the output nodes are proportional to the input voltages applied to the control terminals of the input transistors. By cross-coupling the multiplying branches to the output nodes and subtracting the two output currents, a current is obtained which is proportional to the product of the two input voltages.

Abstract: A clock generating circuit includes a plurality of delay lines connected in cascade, each delay line including two switching elements for letting in or shutting out a clock, and a delay element connected to each of the switching elements. A PLL circuit and a semiconductor device both include the clock generating circuit. The number K of the delay units in each of the delay lines of the clock generating circuit is calculated from:K>?{1/(2.multidot.N.multidot.F.sub.ref)}-(T.sub.mul)!/(T.sub.

Abstract: A device for supplying the on-board system voltage in a bus coupler without a repeater, for coupling to an information and power carrying bus of a bus system, in particular for building systems management. The device includes a coupling circuit having a control input connected to a triggering circuit having inputs for a control criterion. The coupling circuit operates as a constant current source at communications frequencies and as a control circuit together with a triggering circuit at lower frequencies, such as those caused by power consumption. The coupling circuit is effectively connected in series with a reservoir capacitor for tapping the on-board system voltage. The series connection is effectively connected to the bus drivers.