Patents Examined by Thanh Y. Tran
  • Stacked semiconductor dies for semiconductor device assemblies
    Patent number: 11532595
    Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with an opening extending therethrough. The assembly can include a stack of semiconductor dies attached to the substrate. The stack includes a first die attached to a front surface of the substrate, where the first die includes a first bond pad aligned with the opening. The stack also includes a second die attached to the first die such that an edge of the second die extends past a corresponding edge of the first die. The second die includes a second bond pad uncovered by the first die and aligned with the opening. A bond wire formed through the opening couples the first and second bond pads with a substrate bond pad on a back surface of the substrate.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: December 20, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Jungbae Lee
  • Stacked die integrated with package voltage regulators
    Patent number: 11515289
    Abstract: An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 29, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Bharani Chava, Stanley Seungchul Song, Abinash Roy, Jonghae Kim
  • Communication interface structure between processing die and memory die
    Patent number: 11515278
    Abstract: A communication interface structure for connection between dies is provided, including a memory die, processing dies and interconnection routings. The memory die includes a first interface edge, wherein the first interface edge is split into a plurality of interface groups. Each of the processing dies includes a second interface edge. Interconnection routings respectively connect the second interface edges of the processing dies to the interface groups of the memory die.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: November 29, 2022
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chieh Liao, Igor Elkanovich, Hung-Yi Chang, Li-Ken Yeh, Chung-Ling Liou
  • Package structure and manufacturing method thereof
    Patent number: 11495573
    Abstract: A package structure includes a first semiconductor die, a second semiconductor die, a redistribution circuit structure, and a semiconductor device. The redistribution circuit structure has a first surface and a second surface opposite to the first surface, where the first surface is in contact with the first semiconductor die and the second semiconductor die, and the redistribution circuit structure is disposed on and electrically connected to the first semiconductor die and the second semiconductor die. The redistribution circuit structure includes a recess extending from the second surface toward the first surface. The semiconductor device is located in the recess and electrically connected to the first semiconductor die and the second semiconductor die through the redistribution circuit structure.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Semiconductor device package
    Patent number: 11469165
    Abstract: A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: October 11, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Yu-Ying Lee
  • Optical proximity sensor with self-compensation for ambient light and crosstalk using light-to-frequency conversion technique
    Patent number: 11467268
    Abstract: Disclosures of the present invention describe an optical proximity sensor, which is particularly designed to have functionality of canceling an ambient light noise and/or an optical crosstalk noise by using light-to-frequency conversion technique, and comprises: a controlling and processing circuit, a lighting unit, a light receiving unit, an analog adder, a first DAC unit, a second DAC unit, and a light-to-digital conversion (LDC) unit. In the controlling of the controlling and processing circuit, the first DAC unit and the second DAC unit would respectively generate a first compensation current signal and a second compensation current signal to the analog adder, such that a noise signal of ambient light and a noise signal of optical crosstalk existing in an optical current signal of object reflection light would be canceled by the two compensation current signals in the analog adder.
    Type: Grant
    Filed: June 23, 2019
    Date of Patent: October 11, 2022
    Assignees: Dyna Image Corporation, Lite-On Semiconductor Corporation
    Inventors: Wen-Sheng Lin, Sheng-Cheng Lee, Yu-Cheng Su, Peng-Han Chan, Chun-Hsien Lin
  • Integrated circuit package and method
    Patent number: 11469197
    Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chih Chiou, Chen-Hua Yu, Shih Ting Lin, Szu-Wei Lu
  • Chip bonding alignment structure, chip bonding structure and methods for fabricating the same
    Patent number: 11462513
    Abstract: A chip bonding alignment structure includes a semiconductor chip, a metal layer, an etching stop layer, at least one metal bump, a dielectric barrier layer, a silicon oxide layer, and a silicon carbonitride layer. The metal layer is disposed on a bonding surface of the semiconductor chip and has a metal alignment pattern. The etching stop layer covers the bonding surface and the metal layer. The metal bump extends upward from the metal layer and penetrates through the etching stop layer. The dielectric barrier layer covers the etching stop layer and the metal bump. The silicon oxide layer covers the dielectric barrier layer. The silicon carbonitride layer covers the silicon oxide layer.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: October 4, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Chia Yang, Fu-Yu Tsai, Da-Jun Lin, Bin-Siang Tsai
  • Magnetic storage device
    Patent number: 11462680
    Abstract: A magnetic storage device includes a magnetoresistive effect element. The magnetoresistive effect element includes a first ferromagnetic layer; a second ferromagnetic layer; a non-magnetic layer between the first ferromagnetic layer and the second ferromagnetic layer; and a first layer provided at a side of the first ferromagnetic layer opposite to a side of the first ferromagnetic layer at which the non-magnetic layer is provided. The first layer includes a rare-earth element and the first layer has a region including boron (B) at a proportion higher than a proportion of boron (B) in the first ferromagnetic layer.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: October 4, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Daisuke Watanabe, Toshihiko Nagase
  • Semiconductor package and method of fabricating the same
    Patent number: 11456226
    Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Chih-Wei Lin
  • Three-dimensional memory device with backside source contact
    Patent number: 11456290
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and a source contact above the memory stack and in contact with the second semiconductor layer.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: September 27, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Kun Zhang, Linchun Wu, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Method for producing wafers using ultrasound
    Patent number: 11446771
    Abstract: A wafer producing method for producing a wafer from an ingot, the ingot being previously formed with a separation layer along which the wafer is to be separated from the ingot. The wafer producing method includes a first ultrasonic vibration applying step of applying ultrasonic vibration to a given area of the ingot at a high density to thereby form a partially broken portion where a part of the separation layer is broken, a second ultrasonic vibration applying step of applying the ultrasonic vibration to the whole area of the ingot larger than the given area at a low density, after performing the first ultrasonic vibration applying step, thereby forming a fully broken portion where the separation layer is fully broken in such a manner that breaking starts from the partially broken portion, and a separating step of separating the wafer from the ingot along the fully broken portion.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 20, 2022
    Assignee: DISCO CORPORATION
    Inventor: Ryohei Yamamoto
  • Semiconductor device
    Patent number: 11444047
    Abstract: A semiconductor device disclosed herein may include: a semiconductor element including an electrode on a surface of the semiconductor element; and a terminal bonded to the electrode via a bonding material, wherein the electrode may include a protrusion portion that protrudes toward the terminal and is in contact with the bonding material.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 13, 2022
    Assignee: DENSO CORPORATION
    Inventor: Takanori Kawashima
  • Semiconductor memory device and method for driving the same
    Patent number: 11444061
    Abstract: A manufacturing method of a semiconductor device according to an embodiment comprises, bonding a first semiconductor substrate and a second semiconductor substrate to form a stack, filling a first fill material having a first viscosity in a gap located between an outer peripheral portion of the first semiconductor substrate and an outer peripheral portion of the second semiconductor substrate, filling a second fill material having a second viscosity higher than the first viscosity in the gap so as to be adjacent to the first fill material after filling the first fill material in the gap and thinning the second semiconductor.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: September 13, 2022
    Assignee: Kioxia Corporation
    Inventors: Takuro Okubo, Hidekazu Hayashi
  • 3D semiconductor package including memory array
    Patent number: 11444069
    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Han-Jong Chia, Sheng-Chen Wang, Yu-Ming Lin
  • Wafer bonding method
    Patent number: 11437344
    Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Non-volatile memory with different use of metal lines in word line hook up regions
    Patent number: 11424207
    Abstract: To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: August 23, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Shiqian Shao, Fumiaki Toyama
  • Memory die with source side of three-dimensional memory array bonded to logic die and methods of making the same
    Patent number: 11417621
    Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 16, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Masanori Tsutsumi, Sayako Nagamine
  • Semiconductor package having passive support wafer
    Patent number: 11417630
    Abstract: Semiconductor packages including passive support wafers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes a passive support wafer mounted on several active dies. The active dies may be attached to an active die wafer, and the passive support wafer may include a monolithic form to stabilize the active dies and active die wafer during processing and use. Furthermore, the passive support wafer may include a monolith of non-polymeric material to transfer and uniformly distribute heat generated by the active dies.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Digvijay A. Raorane, Ravindranath Vithal Mahajan, Mitul Bharat Modi
  • Electronic module for high power applications
    Patent number: 11410977
    Abstract: An electronic module can include a first integrated device package comprising a first substrate and an electronic component mounted to the first substrate. A first vertical interconnect can be mounted to and electrically connected to the first substrate. The first vertical interconnect can extend outwardly from the first substrate. The electronic module can include a second integrated device package comprising a second substrate and a second vertical interconnect having a first end mounted to and electrically connected to the second substrate. The second vertical interconnect can have a second end electrically connected to the first vertical interconnect. The first and second vertical interconnects can be disposed between the first and second substrates.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 9, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: John D. Brazzle, Frederick E. Beville, Yucheng Ying, Zafer S. Kutlu