Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

Abstract: A memory controller for controlling an operation of a semiconductor memory device including a memory block including a plurality of sub-blocks. The memory controller includes a randomizer. The randomizer includes: seed table storage configured to store a plurality of seed tables respectively corresponding to the plurality of sub-blocks, and to generate a seed, based on sub-block information of received original data; a random sequence generator configured to generate a random sequence, based on the seed generated by the seed table storage; and an operating component configured to generate random data, based on the random sequence and the original data.

Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

Abstract: Disclosed herein is an apparatus that includes a memory cell array, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.

Abstract: This application provides a data writing method and a storage device. The method is applied to a solid-state storage device SSD, and the method includes: receiving a write command, where the write command carries a type of to-be-written data; determining, based on the type of to-be-written data, a type of storage area that is in an SSD and into which the to-be-written data is written, where the SSD includes a plurality of types of storage areas; determining, based on the type of storage area, a target storage area into which the to-be-written data is written; and writing the to-be-written data into the target storage area. In embodiments of this application, data processing efficiency can be improved.

Abstract: A method of manufacturing an array of magnetic random access memory cells includes writing to a magnetic random access memory cell. The writing to a memory cell includes determining an optimum write current for the array of memory cells, and applying the optimum write current to a first memory cell in the array. A first read current is applied to the first memory cell to determine whether a magnetic orientation of the first memory cell has changed in response to applying the optimum write current. A second write current is applied to the first memory cell when the magnetic orientation of the first memory cell has not changed. The second write current is different from the optimum write current. A second read current is applied to the first memory cell to determine whether the magnetic orientation of the first memory cell changed in response to applying the second write current.

Abstract: Provided herein may be a storage device and a method of operating the storage device. A memory device may include a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform an operation on memory cells selected from among the plurality of memory cells, a voltage variation detector configured to generate voltage variation information indicating whether a voltage variation has occurred in a supply voltage during performance of the operation, a power register configured to store the voltage variation information, a status register configured to store status information indicating an operating status of the memory device, and a register output controller configured to update the status information provided from the status register based on the voltage variation information.

Abstract: A method includes performing a quantity of write cycles on memory components. The method can further include monitoring codewords, and, for each of the codewords including a first error parameter value, determining a second error parameter value. The method can further include determining a probability that each of the codewords is associated with a particular one of the second error parameter values at the first error parameter value and determining a quantity of each of the codewords that are associated with each of the determined probabilities. The method can further include determining a statistical boundary of the quantity of each of the codewords and determining a correlation between the quantity of write cycles performed and the corresponding determined statistical boundary of the quantity of each of the codewords.

Abstract: A memory device includes logic to detect the last page written in multi-plane non-volatile memory. The device includes a memory array, and a storage controller. The memory array includes multiple planes and multiple word lines operable on the memory array. The storage controller is configured to divide the word lines into contiguous sub-ranges and assign a subset of the word lines to boundaries of the sub-ranges. Each word line of the subset of word lines is assigned to a page in a different one of the memory planes. The controller operates the subset of word lines to sense a page programmed or erased state from each of the memory planes in parallel.

Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a CAM block configured to store CAM data required for various operations, a page buffer group configured to store the CAM data read from the CAM block through a CAM read operation, an extra register configured to store extra data generated by performing an operation on the CAM data, an operation logic configured to perform an operation of checking a defect in the extra register, registers configured to sequentially store operation data generated through the defect check operation, a fixed register configured to store fixed data obtained through an operation performed to check an error in the CAM data, and core circuits configured to perform the CAM read operation and transmit the operation data and the CAM data to the extra register, the registers, and the fixed register.

Abstract: Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.

Abstract: A memory sub-system configured to adaptively and/or iteratively determine sub-operations of executing a read command to retrieve data from memory cells. For example, after receiving the read command from a processing device of a memory sub-system, a memory device starts an atomic operation of executing the read command in the memory device. The memory device can have one or more groups of memory cells formed on an integrated circuit die and a calibration circuit configured to measure signal and noise characteristics of memory cells in the memory device. During the atomic operation, the calibration circuit generates outputs, based on which a read manager of the memory sub-system identifies sub-operations to be performed in the atomic operation and/or decides to end the atomic operation.

Abstract: Techniques are described for maintaining a stable voltage difference in a memory device, for example, during a critical operation (e.g., a sense operation). The voltage difference to be maintained may be a read voltage across a memory cell or a difference associated with a reference voltage, among other examples. A component (e.g., a local capacitor) may be coupled, before the operation, with a node biased to a first voltage (e.g., a global reference voltage) to sample a voltage difference between the first voltage and a second voltage while the circuitry is relatively quiet (e.g., not noisy). The component may be decoupled from the node before the operation such that a node of the component (e.g., a capacitor) may be allowed to float during the operation. The voltage difference across the component may remain stable during variations in the second voltage and may provide a stable voltage difference during the operation.

Abstract: A memory management operation is executed on a plurality of memory dies of a memory sub-system. The memory sub-system determines whether a first measured current level corresponding to execution of the memory management operation satisfies a condition pertaining to a threshold peak current level. The memory sub-system determines whether a second measured current level corresponding to execution of the memory management operation satisfies the condition pertaining to the threshold peak current level. Mask data is generated identifying the first measured current level and the second measured current level. A request is received from a host system to execute the memory management operation. The memory sub-system performs, based on the mask data, a peak current management action during execution of the memory management operation.

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

Abstract: A memory device includes a plurality of sub-word line drivers with, each sub-word line driver configured to receive a main word line signal and configured to drive a respective local word line to at least one of an active state, a soft-landing state, an off state based on the main word line signal and a phase signal. The memory device also includes a plurality of phase drivers with each phase driver configured to generate the respective phase signal. The memory device can further include a processing device configured to drive the respective local word line to the soft-landing state prior to entering the off state when transitioning from the active state to the off state so as to provide row hammer stress mitigation between adjacent local word lines corresponding to the plurality of sub-word line drivers. Each sub-word line driver includes a diode-connected transistor.

Abstract: A storage device includes a memory device including a plurality of memory cells respectively storing data having a plurality of bits, and a memory controller including an operation block including a plurality of unit circuits executing a predetermined function, and a core block executing a control operation on the plurality of memory cells in response to a command from a host. The core block selects at least portions of the plurality of unit circuits to determine selection unit circuits, and generates a control command specifying an operation order of the selection unit circuits. In the operation block, the selection unit circuits operate by the operation order to determine a control voltage required for the control operation, and store the control voltage in at least one of the memory controller or the memory device.

Abstract: Provided are devices and methods relating to temperature control in a solid state drive (SSD). A SSD (10, 110, 210, 310, 410, 510, 610, 710) including a housing (12, 112, 212, 312, 412, 512, 612, 712) including a plurality of sides surrounding an interior region. The SSD (10, 110, 210, 310, 410, 510, 610, 710) includes at least one vent (14, 114, 214, 314, 414, 514, 614, 714) on the housing (12, 112, 212, 312, 412, 512, 612, 712), the at least one vent (14, 114, 214, 314, 414, 514, 614, 714) configured to be opened and closed in response to a signal.

Abstract: A programmable and reprogrammable processor on a control semiconductor die is disclosed. The processor controls various operations on a memory semiconductor die to which it is bonded, such as read, write, and erase. The processor issues control signals to operate circuits such as voltage regulators, sense amplifiers, and data latches. Because the processor is reprogrammable, it is possible to modify the operation of the circuits. For example, the processor can execute updated instructions to control the voltage regulators to modify the timing and/or magnitude of voltages applied to control lines in the memory semiconductor die. In one aspect, a page mapping scheme is updated in order to more evenly distribute a bit error rate (BER) across the pages. In one aspect, a read equalization scheme is updated. In one aspect, a technique for reading soft bits is updated.