Patents Examined by Thong Q. Le
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Patent number: 11397544Abstract: A neuromorphic memory element comprises a memristor, a plurality of the neuromorphic memory elements and a method for operating the same may be provided. The memristor comprises an input signal terminal, an output signal terminal, and a control signal terminal, and a memristive active channel comprising a phase change material. The memristive active channel extends longitudinal between the input signal terminal and the output signal terminal, and a control signal voltage at the control signal terminal is configured to represent volatile biological neural processes of the neuromorphic memory element, and a bias voltage between the input signal terminal and the output signal terminal is configured to represent non-volatile biological neural processes of the neuromorphic memory element.Type: GrantFiled: November 10, 2020Date of Patent: July 26, 2022Assignee: International Business Machines CorporationInventors: Ghazi Sarwat Syed, Abu Sebastian, Timoleon Moraitis, Benedikt Kersting
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Patent number: 11393544Abstract: An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.Type: GrantFiled: February 26, 2021Date of Patent: July 19, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Qiang Tang, Xiang Fu
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Patent number: 11393530Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.Type: GrantFiled: September 24, 2020Date of Patent: July 19, 2022Assignee: Micron Technology, Inc.Inventor: Jun Liu
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Patent number: 11386958Abstract: Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.Type: GrantFiled: August 31, 2020Date of Patent: July 12, 2022Assignee: Micron Technology, Inc.Inventor: Koji Sakui
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Patent number: 11372591Abstract: A semiconductor system includes a memory controller and a memory apparatus. The memory controller provides at least first to third command address signals. The memory apparatus performs a burst read operation based on the first and second command address signals, and terminates the burst read operation by receiving the third command address signal twice. The memory apparatus continuously initializes an internal circuit that is performing the burst read operation in a section the third command address signal is received twice.Type: GrantFiled: January 25, 2021Date of Patent: June 28, 2022Assignee: SK hynix Inc.Inventors: Seung Wook Oh, Chang Hyun Kim, Young Jae An, Woong Rae Kim
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Patent number: 11362268Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; a magnetic layer over the substrate; a magnetic tunnel junction (MTJ) cell over the magnetic layer; and a non-magnetic conductive layer between the magnetic layer and the MTJ cell. An associated method for fabricating the semiconductor structure is also disclosed.Type: GrantFiled: May 19, 2020Date of Patent: June 14, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chwen Yu, Shy-Jay Lin
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Patent number: 11360695Abstract: Methods, apparatuses, and systems related to combining and utilizing multiple memory circuits having complementary characteristics are described. An apparatus may include a first memory circuit having a first characteristic and a second memory circuit having a second characteristic. Contact pads of the first and second memory circuits may be connected in parallel and to a common interface configured to communicate data between the apparatus and an external device.Type: GrantFiled: September 16, 2020Date of Patent: June 14, 2022Assignee: Micron Technology, Inc.Inventors: Hyun Yoo Lee, Kang-Yong Kim
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Patent number: 11361826Abstract: A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.Type: GrantFiled: July 6, 2020Date of Patent: June 14, 2022Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Sungkwon Lee, Venkatraman Prabhakar
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Patent number: 11361806Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.Type: GrantFiled: August 28, 2020Date of Patent: June 14, 2022Assignee: Micron Technology, Inc.Inventor: Eric S. Carman
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Patent number: 11355193Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.Type: GrantFiled: October 6, 2020Date of Patent: June 7, 2022Assignee: KIOXIA CORPORATIONInventors: Yasuhiro Shiino, Eietsu Takahashi
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Patent number: 11354067Abstract: A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.Type: GrantFiled: August 5, 2020Date of Patent: June 7, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Kalyan Chakravarthy C. Kavalipurapu, Chang H. Siau, Shigekazu Yamada
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Patent number: 11348638Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.Type: GrantFiled: August 24, 2020Date of Patent: May 31, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng
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Patent number: 11347436Abstract: A storage device includes a nonvolatile memory device having a plurality of memory cells and a storage controller. Each memory cell is set to one of a plurality of memory cell states, wherein distinct subsets of the memory cell states are associated with one of a plurality of data sets. The storage controller accesses data stored in one of the memory cells in a first state, performs a multiplier-accumulator (MAC) operation on the data, and sets the one memory cell to a second state corresponding to a result of the MAC operation to perform an in-place update.Type: GrantFiled: August 10, 2020Date of Patent: May 31, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Doo Hyun Kim, Jong-Hoon Lee
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Patent number: 11342025Abstract: A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.Type: GrantFiled: July 20, 2020Date of Patent: May 24, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Wen Tseng, Tsung-Yu Yang, Chung-Jen Huang
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Patent number: 11335413Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current in open blocks during read operations using read voltage ramp rate control. The controller determines whether a block is open or closed. If the block is closed, the controller causes a read voltage to be applied to one of the block's word lines at a first ramp rate. If the block is open, the controller causes a read voltage to be applied to another of the block's word lines at a slower, second ramp rate. The controller further causes a read voltage to be applied to another word line of the open block at a different, third ramp rate. Thus, read voltages for open blocks may ramp slower than read voltages for closed blocks, as well as ramp at different rates for different word lines in open blocks.Type: GrantFiled: May 29, 2020Date of Patent: May 17, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yu-Chung Lien, Huai-Yuan Tseng, Deepanshu Dutta
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Patent number: 11309045Abstract: An integrated memory device can include an array of memory cells with decoding and sensing circuitry, a memory controller, read and write circuitry associated to the sensing circuitry, logic circuit portions in the read and write circuitry including at least a logic element receiving a data stream on a data input and a clock signal on a clock input, and a programmable or trimmable delay element or circuit upstream to the data input or the clock input for self trimming the internal timing of said at least a logic element by aligning in time the clock signal and/or the data stream. Operating parameters of the integrated circuit can be set for self trimming an internal timing of the integrated circuit.Type: GrantFiled: May 31, 2019Date of Patent: April 19, 2022Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Alberto Troia
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Patent number: 11307767Abstract: A system-on-chip (SoC) includes a system memory, a memory controller, and a memory management system coupled therebetween. The memory management system is configured to receive, from the memory controller, a first control signal that is indicative of a memory operation associated with the system memory, and output and provide a second control signal to the system memory to control an execution of the memory operation. The second control signal is outputted such that when the memory operation corresponds to a first read operation, the first read operation is executed with the system memory, and when the memory operation corresponds to a first write operation, a second read operation is executed with the system memory followed by the first write operation. Thus, the memory management system prevents memory corruption of the system memory when an asynchronous reset event is detected in the SoC.Type: GrantFiled: October 15, 2020Date of Patent: April 19, 2022Assignee: NXP USA, INC.Inventors: Nidhi Sinha, Dinesh Joshi, Akshay Kumar Pathak
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Patent number: 11294836Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.Type: GrantFiled: October 19, 2020Date of Patent: April 5, 2022Assignee: Micron Technology, Inc.Inventors: Matthew A. Prather, Frank F. Ross, Randall J. Rooney
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Patent number: 11282580Abstract: A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory having a plurality of wordlines. The controller circuit is configured to program, with foggy-fine programming, a first portion of the plurality of wordlines to store first program data, program, with the foggy-fine programming, one or more wordlines of the plurality of wordlines in a non-fine state, the one or more wordlines neighboring the first portion, and program, with the foggy-fine programming, a second portion of the plurality of wordlines to store second program data, the second portion neighboring the one or more wordlines.Type: GrantFiled: May 29, 2020Date of Patent: March 22, 2022Assignee: Western Digital Technologies, Inc.Inventors: Mayank Gupta, Phani Raghavendra Yasasvi Gangavarapu, Arun Balakrishnan
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Patent number: 11282858Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.Type: GrantFiled: November 3, 2020Date of Patent: March 22, 2022Assignee: KIOXIA CORPORATIONInventors: Go Oike, Tsuyoshi Sugisaki
