Abstract: A method of inspecting a wafer quality includes injecting ions into a wafer using an ion beam in an ion implantation process, collecting data about the ion beam by using a Faraday cup, extracting first data from the data about the ion beam, extracting a wafer section from the first data, calculating a feature value of a wafer from the wafer section, and evaluating a quality of the wafer by comparing the feature value with a predetermined threshold or range.

Abstract: A semiconductor structure includes a plurality of first dies, a second die disposed over each of the first dies, and a dielectric material surrounding the first dies and the second die. The second dies overlaps a portion of each of the first dies. A dimension of the second die is different from a dimension of the first dies.

Abstract: Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages.

Abstract: Embodiments of three-dimensional (3D) memory devices have a hydrogen blocking layer and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, an array of NAND memory strings each extending vertically through the memory stack, a plurality of logic process-compatible devices above the array of NAND memory strings, a semiconductor layer above and in contact with the logic process-compatible devices, a pad-out interconnect layer above the semiconductor layer, and a hydrogen blocking layer vertically between the semiconductor layer and the pad-out interconnect layer and configured to block outgassing of hydrogen.

Abstract: A highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics, and a manufacturing method thereof. In the manufacturing method of the semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region is an oxide semiconductor layer, heat treatment which reduces impurities such as moisture to improve the purity of the oxide semiconductor layer and oxidize the oxide semiconductor layer (heat treatment for dehydration or dehydrogenation) is performed. Not only impurities such as moisture in the oxide semiconductor layer but also those existing in a gate insulating layer are reduced, and impurities such as moisture existing in interfaces between the oxide semiconductor layer and films provided over and under and in contact with the oxide semiconductor layer are reduced.

Abstract: A land grid array semiconductor device is disclosed which is configured for removable insertion to and from a host device. The land grid array semiconductor device may include a first set of one or more contact fingers on the first surface of the land grid array semiconductor device, and a second set of one or more contact fingers on the second surface of the land grid array semiconductor device. In order to electrically couple the second set of one or more contact fingers, one or more electrical connectors may be provided physically extending between the second set of one or more contact fingers and at least one of the substrate and the at least one semiconductor die.

Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.

Abstract: A multi-wavelength light emitting device is manufactured by forming first and second epitaxial materials overlying first and second surface regions. The first and second epitaxial materials are patterned to form a plurality of first and second epitaxial dice. At least one of the first plurality of epitaxial dice and at least one of the second plurality of epitaxial dice are transferred from first and second substrates, respectively, to a carrier wafer by selectively etching a release region, separating from the substrate each of the epitaxial dice that are being transferred, and selectively bonding to the carrier wafer each of the epitaxial dice that are being transferred. The transferred first and second epitaxial dice are processed on the carrier wafer to form a plurality of light emitting devices capable of emitting at least a first wavelength and a second wavelength.

Abstract: There is provided a film-forming apparatus, comprising: a process container in which a vacuum atmosphere is formed; a rotary table installed in the process container, the rotary table having substrate mounting regions formed on a side of a top surface of the rotary table and configured to mount a plurality of substrates, and the rotary table including a rotary mechanism configured to rotate the substrate mounting regions around a rotary shaft; a heating mechanism configured to heat the substrates mounted on the substrate mounting regions; a gas supply part installed to face a moving region where the substrates move when the rotary table rotates and including gas discharge holes formed to cross the moving region, the gas discharge holes being configured to discharge a first film-forming gas and a second film-forming gas; and an exhaust part configured to exhaust an interior of the process container.

Abstract: A method for forming a V-NAND device is disclosed. Specifically, the method involves deposition of at least one of semiconductive material, conductive material, or dielectric material to form a channel for the V-NAND device. In addition, the method may involve a pretreatment step where ALD, CVD, or other cyclical deposition processes may be used to improve adhesion of the material in the channel.

Abstract: A method is disclosed, which comprises forming a mid layer over a mask stack that is over a device layer of a substrate; forming a first buffer layer on the mid layer and a plurality pairs of first linear patterns over the first buffer layer; deposing a spin on hard mask layer filling between the first linear patterns; forming a second buffer layer on the spin on hard mask layer and a plurality of second linear patterns on the second buffer layer that projectively intercepts the first linear patterns; performing a mid layer opening process by concurrently etching the second buffer layer, the spin on hard mask layer, and the first buffer layer through the first and the second linear patterns to partially expose the mid layer; and etching the exposed portions of the mid layer to form a grid-type pattern over the mask stack.

Abstract: A semiconductor device includes a first chip including a first substrate, a first cell array, a first metal wire, and a first bonding structure, wherein the first bonding structure includes a first through portion that passes through the first metal wire and a first bonding portion that is formed in the first substrate, and a second chip, bonded to the first chip, including a second substrate, a second cell array, a second metal wire, and a second bonding structure, wherein the second bonding structure includes a second through portion that passes through the second metal wire and a second bonding portion that is formed in the second substrate, and bonded to the first chip. The first bonding portion of the first chip is configured to be bonded to the second through portion of the second chip.

Abstract: A solid-state imaging device includes a first and second pixel regions. In the first pixel region, a photoelectric conversion unit, a floating diffusion region (FD), and a transferring transistor are provided. In the second pixel region, an amplifying transistor, and a resetting transistor are provided. A first element isolation portion is provided in the first pixel region, while a second element isolation portion is provided in the second pixel region. An amount of protrusion of an insulating film into a semiconductor substrate in the first element isolation portion is smaller, than that in the second element isolation portion.

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer.

Abstract: A display device, and method for manufacture, having a substrate; a first thin film transistor (TFT) on the substrate, the first TFT having a first active layer, a first gate insulator, and a first gate electrode; a second TFT on the substrate, the second TFT having a second active layer, a second gate insulator and a second gate electrode. The first gate insulator is disposed between the first gate electrode and the first active layer, and the first gate insulator is in contact with the first active layer. The second gate insulator is disposed between the second gate electrode and the second active layer, and the second gate insulator is in contact with the second active layer. The first active layer is a different material than said second active layer, and a hydrogen concentration of the second gate insulator is less than a hydrogen concentration of the first gate insulator.

Abstract: A plurality of dies includes a gallium and nitrogen containing substrate having a surface region and an epitaxial material formed overlying the surface region. The epitaxial material includes an n-type cladding region, an active region having at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active region. The epitaxial material is patterned to form the plurality of dies on the surface region, the dies corresponding to a laser device. Each of the plurality of dies includes a release region composed of a material with a smaller bandgap than an adjacent epitaxial material. A lateral width of the release region is narrower than a lateral width of immediately adjacent layers above and below the release region to form undercut regions bounding each side of the release region. Each die also includes a passivation region extending along sidewalls of the active region.

Abstract: A semiconductor package structure includes a wiring structure, a semiconductor module, a protection layer and a plurality of outer conductive vias. The wiring structure includes at least one dielectric layer and at least one redistribution layer. The semiconductor module is electrically connected to the wiring structure. The semiconductor module has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The protection layer covers the lateral surface of the semiconductor module and a surface of the wiring structure. The outer conductive vias surround the lateral surface of the semiconductor module, electrically connect to the wiring structure, and extend through a dielectric layer of the wiring structure and the protection layer.

Abstract: A method includes producing a semiconductor arrangement having a semiconductor layer, a first insulation layer arranged on the semiconductor layer and facing a first surface of the semiconductor arrangement, and an insulating via extending in a vertical direction through the semiconductor layer as far as the first insulation layer, the insulating via surrounding a region of the semiconductor layer in a ring-shaped fashion. The method further includes permanently securing a first carrier to the first surface of the semiconductor arrangement.

Abstract: Methods for conformal radical oxidation of structures are provided. The method comprises positioning a substrate in a processing region of a processing chamber. The method further comprises flowing hydrogen gas into a precursor activator at a first flow rate, wherein the precursor activator is fluidly coupled with the processing region. The method further comprises flowing oxygen gas into the precursor activator at a second flow rate. The method further comprises flowing argon gas into the precursor activator at a third flow rate. The method further comprises generating a plasma in the precursor activator from the hydrogen gas, oxygen gas, and argon gas. The method further comprises flowing the plasma into the processing region. The method further comprises exposing the substrate to the plasma to form an oxide film on the substrate, wherein a growth rate of the oxide film is controlled by adjusting the third flow rate.