Patents Examined by Timor Karimy
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Patent number: 11355374Abstract: A receiving means for receiving and mounting of wafers, comprised of a mounting surface, mounting means for mounting a wafer onto the mounting surface and compensation means for active, locally controllable, compensation of local and/or global distortions of the wafer.Type: GrantFiled: November 30, 2020Date of Patent: June 7, 2022Assignee: EV Group E. Thallner GmbHInventors: Markus Wimplinger, Thomas Wagenleitner, Alexander Filbert
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Patent number: 11348900Abstract: A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.Type: GrantFiled: June 11, 2020Date of Patent: May 31, 2022Assignee: MediaTek Inc.Inventors: Tzu-Hung Lin, Yu-Hua Huang, Wei-Che Huang, Ming-Tzong Yang
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Patent number: 11348869Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.Type: GrantFiled: November 22, 2020Date of Patent: May 31, 2022Assignee: Unimicron Technology Corp.Inventors: Chien-Chou Chen, Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
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Patent number: 11342268Abstract: In one example, an electronic assembly comprises a first semiconductor device and a second semiconductor device. Each of the first semiconductor device and the second semiconductor devices comprises a substrate comprising a top surface and a conductive structure, an electronic component over the top surface of the substrate, a dielectric material over the top surface of the substrate and contacting a side of the electronic component, a substrate tab at an end of substrate and not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate tab, and an interconnect electrically coupled to the conductive structure at the substrate tab of the first semiconductor device and the conductive structure at the substrate tab of the second semiconductor device. Other examples and related methods are also disclosed herein.Type: GrantFiled: January 29, 2020Date of Patent: May 24, 2022Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Ji Young Chung, Seung Chul Jang, Ron Huemoeller
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Patent number: 11335642Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.Type: GrantFiled: December 29, 2017Date of Patent: May 17, 2022Assignee: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
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Patent number: 11335645Abstract: A high-frequency module 1 includes: a substrate 2; a first component 4 mounted on an upper surface 2a of the substrate 2; a second component 5 mounted on a lower surface 2b of the substrate 2; an upper sealing resin layer 6 and a lower sealing resin layer 7; a conductor pin 8; and a shield layer 9. The conductor pin 8 includes a terminal portion 8a exposed from a lower surface 7a of the lower sealing resin layer 7 and connected to a ground electrode of an outer substrate, and a shield connection portion 8b exposed from a side surface 7b of the lower sealing resin layer 7 and connected to the shield layer 9. As a result of the terminal portion 8a of the conductor pin 8 being connected to the ground electrode, the shield layer 9 is connected to a ground potential with the shortest distance therebetween.Type: GrantFiled: March 3, 2020Date of Patent: May 17, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yoshihito Otsubo, Osamu Yamaguchi
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Patent number: 11328972Abstract: A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one chip is bonded over the temporary bonding layer.Type: GrantFiled: December 31, 2018Date of Patent: May 10, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Yu Lee, Ying-Hao Kuo, Kuo-Chung Yee
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Patent number: 11319208Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.Type: GrantFiled: July 28, 2020Date of Patent: May 3, 2022Assignee: XINTEC INC.Inventors: Tsang-Yu Liu, Chaung-Lin Lai, Shu-Ming Chang
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Patent number: 11322586Abstract: A semiconductor device capable of suppressing the calorific value at the central portion of a wire bonding area is provided. A semiconductor device includes a plurality of IGBT cells in a cell area. An emitter electrode serves as a current path when a plurality of IGBT cells are in conductive state, and is formed to cover a plurality of IGBT cells. A wire is bonded to the emitter electrode. A dummy cell which does not perform a bipolar operation, is formed at least below a central portion of a wire bonding area which is an area at which the wire and the emitter electrode are bonded.Type: GrantFiled: November 13, 2019Date of Patent: May 3, 2022Assignee: Mitsubishi Electric CorporationInventor: Shunsuke Sakamoto
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Patent number: 11302675Abstract: A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the at least one side surface. The first adhesive layer and the first resin layer contact each other.Type: GrantFiled: August 31, 2020Date of Patent: April 12, 2022Assignee: KIOXIA CORPORATIONInventors: Takeori Maeda, Yuusuke Takano, Soichi Homma
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Patent number: 11302673Abstract: A semiconductor device is disclosed including one or more stacks of semiconductor dies vertically molded together in an encapsulated block. The semiconductor dies may comprise memory dies, or memory dies and a controller die.Type: GrantFiled: March 13, 2020Date of Patent: April 12, 2022Assignee: Western Digital Technologies, Inc.Inventors: Xuyi Yang, Cong Zhang, Chin-Tien Chiu
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Patent number: 11296052Abstract: A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates.Type: GrantFiled: September 30, 2017Date of Patent: April 5, 2022Assignee: Intel CorporationInventors: Preston T. Meyers, Javier A. Falcon, Shawna M. Liff, Joe R. Saucedo, Adel A. Elsherbini, Albert S. Lopez, Johanna M. Swan
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Patent number: 11282759Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, a first semiconductor device, a second semiconductor device, and a protective layer. The interposer substrate is disposed over the package substrate. The first semiconductor device and the second semiconductor device are disposed over the interposer substrate, wherein the first semiconductor device and the second semiconductor device are different types of electronic devices. The protective layer is formed over the interposer substrate to surround the first semiconductor device and the second semiconductor device. The second semiconductor device is exposed from the protective layer and the first semiconductor device is not exposed from the protective layer.Type: GrantFiled: March 12, 2020Date of Patent: March 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Cheng Hsu, Shin-Puu Jeng, Shuo-Mao Chen
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Patent number: 11270914Abstract: Electronic devices and methods to form electronic devices having a self-aligned via are described. An adhesion enhancement layer is utilized to promote adhesion between the conductive material and the sidewalls of the at least one via opening. The self-aligned vias decrease via resistance and reduce the potential to short to the wrong metal line.Type: GrantFiled: January 14, 2021Date of Patent: March 8, 2022Assignee: Applied Materials Inc.Inventors: Suketu Arun Parikh, Mihaela Balseanu
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Patent number: 11270990Abstract: A contoured package on package joint and a method for making the same are disclosed herein. A method for forming a device comprises providing a substrate having a package land and forming a mounting stud on the package land. A molded underfill is applied to the substrate and in contact with the mounting stud. A contoured stud surface is formed on the mounting stud is contoured and connecting member attached to the contoured stud surface with a second package attached to the connecting member. The connecting member may be solder and have a spherical shape. The contoured stud surface may be etched or mechanically formed to have a hemispherical shape conforming to the connecting member shape.Type: GrantFiled: May 29, 2020Date of Patent: March 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jiun Yi Wu
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Patent number: 11266014Abstract: Embodiments of the invention include LED lighting systems and methods. For example, in some embodiments, an LED lighting system is included. The LED lighting system can include a flexible layered circuit structure that can include a top thermally conductive layer, a middle electrically insulating layer, a bottom thermally conductive layer, and a plurality of light emitting diodes mounted on the top layer. The LED lighting system can further include a housing substrate and a mounting structure. The mounting structure can be configured to suspend the layered circuit structure above the housing substrate with an air gap disposed in between the bottom thermally conductive layer of the flexible layered circuit structure and the housing substrate. The distance between the layered circuit structure and the support layer can be at least about 0.5 mm. Other embodiments are also included herein.Type: GrantFiled: June 24, 2019Date of Patent: March 1, 2022Assignee: Metrospec Technology, L.L.C.Inventors: Henry V. Holec, Wm. Todd Crandell
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Patent number: 11263424Abstract: Microelectromechanical (MEMS) devices and associated methods are disclosed. Piezoelectric MEMS transducers (PMUTs) suitable for integration with complementary metal oxide semiconductor (CMOS) integrated circuit (IC), as well as PMUT arrays having high fill factor for fingerprint sensing, are described.Type: GrantFiled: February 28, 2020Date of Patent: March 1, 2022Assignee: INVENSENSE, INC.Inventors: Julius Ming-Lin Tsai, Mike Daneman, Sanjiv Kapoor
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Patent number: 11257516Abstract: The present technology relates to a storage device that realizes both a high information retention property and a low power consumption. A storage device includes a fixed layer, a storage layer, an intermediate layer, and a heat generation layer. The fixed layer includes a first ferromagnetic layer that includes a fixed perpendicular magnetization. The storage layer includes a second ferromagnetic layer that includes a perpendicular magnetization invertible by a spin injection. The intermediate layer is formed of an insulator and is arranged between the storage layer and the fixed layer. The heat generation layer is formed of a resistance heating element and is arranged in at least one of the storage layer and the fixed layer. With this configuration, it becomes possible to provide a storage device that realizes both a high information retention property and a low power consumption.Type: GrantFiled: February 6, 2020Date of Patent: February 22, 2022Assignee: Sony CorporationInventors: Kazutaka Yamane, Hiroyuki Uchida, Yutaka Higo, Hiroyuki Ohmori, Kazuhiro Bessho, Masanori Hosomi
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Patent number: 11257790Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.Type: GrantFiled: March 10, 2020Date of Patent: February 22, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Kurtis Leschkies, Han-Wen Chen, Steven Verhaverbeke, Giback Park, Kyuil Cho, Jeffrey L. Franklin, Wei-Sheng Lei
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Patent number: 11246230Abstract: Configurable smart object systems with methods of making modules and contactors are provided. Example systems implement machine learning based on neural networks that draw low power for use in smart phones, watches, drones, automobiles, and medical devices. Example assemblies can be configured from pluggable, interchangeable modules that have compatible ports for interconnecting and integrating functionally dissimilar sensor systems. An example method includes mounting an element of a configurable machine learning assembly on a substrate, creating at least one fold in the substrate, folding the substrate at the fold into a housing of a module of the configurable machine learning assembly, and adding a molding material to the housing to at least partially fill the module of the configurable machine learning assembly. The example module construction may also form contactors on folded edges of the module for making physical and electrical contact with other modules of the smart object machine learning assembly.Type: GrantFiled: September 26, 2018Date of Patent: February 8, 2022Assignee: Xcelsis CorporationInventors: Belgacem Haba, Ilyas Mohammed, Gabriel Z. Guevara, Min Tao