Abstract: Configurable smart object systems with methods of making modules and contactors are provided. Example systems implement machine learning based on neural networks that draw low power for use in smart phones, watches, drones, automobiles, and medical devices. Example assemblies can be configured from pluggable, interchangeable modules that have compatible ports for interconnecting and integrating functionally dissimilar sensor systems. An example method includes mounting an element of a configurable machine learning assembly on a substrate, creating at least one fold in the substrate, folding the substrate at the fold into a housing of a module of the configurable machine learning assembly, and adding a molding material to the housing to at least partially fill the module of the configurable machine learning assembly. The example module construction may also form contactors on folded edges of the module for making physical and electrical contact with other modules of the smart object machine learning assembly.

Abstract: Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.

Abstract: A semiconductor package structure includes a first semiconductor die, a second semiconductor die, a third semiconductor die and an external contact. The second semiconductor die is disposed adjacent to the first semiconductor die. The third semiconductor die electrically connects the first semiconductor die and the second semiconductor die. The external contact is electrically connected to the third semiconductor die. An electrical path between the third semiconductor die and the external contact extends through a space between the first semiconductor die and the second semiconductor die.

Abstract: Disclosed is a process whereby diverse classes of materials can be 3D printed and fully integrated into device components with active properties. An exemplary embodiment shows the seamless interweaving of five different materials, including (1) emissive semiconducting inorganic nanoparticles, (2) an elastomeric matrix, (3) organic polymers as charge transport layers, (4) solid and liquid metal leads, and (5) a UV-adhesive transparent substrate layer, demonstrating the integrated functionality of these materials. Further disclosed is a device for printing these fully integrated 3D devices.

Abstract: Example embodiments relate to an image sensor configured to achieve a high photoelectric conversion efficiency and a low dark current. The image sensor includes first and second electrodes, a plurality of photodetection layers provided between the first and second electrodes, and an interlayer provided between the photodetection layers. The photodetection layers convert incident light into an electrical signal and include a semiconductor material. The interlayer includes a metallic or semi metallic material having anisotropy in electrical conductivity.

Abstract: A driver board assembly includes first and second substrates, one or more power device assemblies and a cooling manifold. At least one jet impingement assembly is formed on a first surface of the first substrate and includes an impingement receiving portion that is at least partially circumferentially surrounded by a plurality of fluid microchannels that extend radially from the impingement receiving portion along the first surface. The second substrate is bonded onto the first substrate. The second substrate surface has a recess. The plurality of receiving contours are etched within the first surface of the first substrate. The one or more power device assemblies are bonded into the recess of the second substrate. A first cooling surface of the cooling manifold is bonded to the first surface such that the first cooling surface bonds within the plurality of receiving contours within the first surface of the first substrate.

Abstract: A mask blank, which is capable of being formed with high transfer accuracy when a hard mask film pattern is used as a mask, and even when the mask blank includes a chromium-based light shielding film. A light-semitransmissive film, a light shielding film, and a hard mask film are laminated in the stated order on a transparent substrate. The light-semitransmissive film contains silicon, and the hard mask film contains any one or both of silicon and tantalum. The light shielding film has a laminate structure of a lower layer and an upper layer, and contains chromium. The upper layer has a content of chromium of 65 at % or more, and a content of oxygen of less than 20 at %, and the lower layer has a content of chromium of less than 60 at %, and a content of oxygen of 20 at % or more.

Abstract: A semiconductor package may include: a first chip stack including a plurality of first semiconductor chips stacked in a vertical direction; and first vertical interconnectors electrically coupled to the plurality of first semiconductor chips, respectively, and extended in the vertical direction, wherein each of the other first semiconductor chips, except at least the uppermost first semiconductor chip from among the plurality of first semiconductor chips includes: an active surface defined by two side surfaces of the first semiconductor chip in a first direction and two side surfaces of the first semiconductor chip in a second direction crossing the first direction; a first one-side chip pad disposed at an edge of the active surface, which is close to one side surface in the first direction; a first other-side chip pad disposed at an edge of the active surface, which is close to an other side surface in the first direction; and a first redistribution pad electrically coupled to the first other-side chip pad,

Abstract: The invention concerns a heterojunction field-effect transistor comprising a stack of first and second III-N type semiconducting layers forming an electron gas or hole layer; a first conduction electrode in electrical contact with the gas layer and a second conduction electrode; a separation layer positioned vertically in line with the first electrode and under the second semiconducting layer; a third semiconducting layer arranged under the separation layer and in electrical contact with the second electrode; a conductive element in electrical contact with the gas layer and electrically connecting the third semiconducting layer and the gas layer; and a control gate positioned between the conductive element and the first conduction electrode.

Abstract: Reconstructed 3DIC structures and methods of manufacture are described. In an embodiment, one or more dies in each package level of a 3DIC are both functional chips and/or stitching devices for two or more dies in an adjacent package level. Thus, each die can function as a communication bridge between two other dies/chiplets in addition to performing a separate chip core function.

Abstract: A chip on film package includes a base substrate, an input line, an integrated circuit (IC) chip and an output line. The input line is disposed on the base substrate. The IC chip is electrically connected to the input line. The output line includes a main output and a sub output line. The main output line is electrically connected to the IC chip and extends in a first direction from the IC chip. The sub output line is electrically connected to the IC chip. The sub output line includes at least six bending parts, and is extended in the first direction.

Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

Abstract: One embodiment includes a computer interconnect system. The system includes a first cable comprising a first superconducting signal line formed from a superconductor material to propagate at least one signal and a second cable comprising a second superconducting signal line formed from the superconductor material to propagate the respective at least one signal. The system also includes an interconnect structure configured to contact each of the first and second cable and comprising a third superconducting signal line formed from the superconductor material and configured to propagate the respective at least one signal between the respective first and second superconducting signal line. The system further includes at least one interconnect contact disposed on the first, second, and third at least one superconducting signal line at a contact portion between each of the at least one first and third superconducting signal lines and the at least second and third superconducting signal lines.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.

Abstract: An integrated circuit has an isolation capacitor structure that reduces the risk of breakdown from high electric fields at the edge of the top metal plate of the capacitor. The capacitor structure includes a bottom metal plate above a substrate. A first dielectric layer of a first dielectric material is formed between the bottom metal plate and the top metal plate. The capacitor structure also includes a thin narrow ring formed of a second dielectric material located under a portion of the top metal plate. The second dielectric material has a higher dielectric constant than the first dielectric material. The thin narrow ring follows the shape of the edge of the top metal plate with a portion of the ring underneath the top metal plate and a portion outside the edge of the top metal plate to thereby be located at a place of the maximum electric field.

Abstract: A main Insulated Gate Bipolar Transistor (IGBT) and a sense IGBT may have a sense resistor connected between a sense emitter of the sense IGBT and a main emitter of the main IGBT. Back-to-back Zener diodes may be connected between a sense gate of the sense IGBT and the sense emitter, and configured to clamp a voltage between the sense gate and the sense emitter during an electrostatic discharge (ESD) event.

Abstract: A substrate treatment apparatus according to an embodiment of the present invention includes a chamber, a stage, a gas discharger, a plasma generator, and a rotation mechanism. The stage supports a semiconductor substrate in the chamber. The gas discharger discharges a film formation gas toward the semiconductor substrate from a position opposing the stage. The plasma generator is provided on the gas discharger and generates plasma in the chamber during discharge of the film formation gas. The rotation mechanism rotates the stage during generation of the plasma.

Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.

Abstract: Disclosed is a temporary protective film for semiconductor sealing molding 10 including a support film 1; and an adhesive layer 2 provided on the support film 1 and containing an acrylic rubber. A solid shear modulus at 200° C. of the temporary protective film for semiconductor sealing molding 10 may be 5.0 MPa or higher.