Abstract: Embodiments include a system for minimizing storage space required for tracking load instructions through a pipeline in a processor. Store instructions are tracked in a separate queue and only load instructions that require speculation on data or addresses are tracked in a load table and flagged in the reorder buffer. This system improves system performance by reducing energy and space requirements.

Abstract: A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.

Abstract: A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.

Abstract: Microprocessor arrangement and a method for operating a microprocessor arrangement, where the microprocessor arrangement has an execution unit for controlling a program cycle and for processing arithmetic and logic operations, a working register which stores a result of an operation and which is coupled to a control element in the execution unit, a flag register which indicates information about the result of the operation using flag bits, and combinational logic elements which are connected to the working register, wherein the combinational logic elements are controlled such that the state of the flag bits in the flag register is updated after the executed operation only if execution of one of subsequent operations within the program cycle requires a status of the flag bits.

Abstract: RAW aliasing can be predicted with register bypassing based at least in part on execution displacement alias prediction. Repeated aliasing between read and write operations (e.g., within a loop), can be reliably predicted based on displacement between the aliasing operations. Performing register bypassing for predicted to alias operations facilitates faster RAW bypassing and mitigates the performance impact of aliasing read operations. The repeated aliasing between operations is tracked along with register information of the aliasing write operations. After exceeding a confidence threshold, an instance of a read operation is predicted to alias with an instance of a write operation in accordance with the previously observed repeated aliasing. Based on displacement between the instances of the operations, the register information of the write operation instance is used to bypass data to the read operation instance.

Abstract: Method and system for controlling the dynamic latency of an arithmetic logic unit (ALU). In one embodiment, the identification of the destination operand of an instruction is stored in a temporary register ID/thread control ID pair pipeline if the destination operand is a temporary register. Furthermore, each source operand of an instruction is checked against the identifications stored in a group of temporary register ID/thread control ID pipelines. If a source operand is matched to an identification stored in the temporary register ID/thread control ID pipelines, the ALU does not execute the instruction until the matched identification is no longer matched in the pipelines.

Abstract: Systems, methodologies, media, and other embodiments associated with simulating a processor performance state by controlling a thermal management signal are described. One exemplary system embodiment includes a data structure for storing bit patterns that facilitate controlling a GPIO (General Purpose Input Output) block and addresses of locations to which the bit patterns can be written. The example system may also include a logic configured to receive a request to produce a performance state in a processor and to cause a frequency and voltage to be established in the processor in response to a thermal management signal being generated in response to writing the bit pattern(s) to the address(es).

Abstract: A multi-mode predictor for a processor having a plurality of prediction modes is disclosed. The prediction modes are used to predict non-binary values. The predictor is a multi-mode predictor comprising a per-IP (“PIP”) table and a next value table. The PIP table includes a plurality of PIP information fields and the next value table includes a plurality of fields. The multi-mode predictor also includes a plurality of prediction modes. The processor includes a set of instructions that index the PIP table to provide a valid signal. The processor also includes a set of predicted values for the set of instructions. The set of predicted values is stored in the PIP table and the next value table. According to the valid signal a hit/miss condition in the next value table, a predicted value is selected from the PIP table or the next value table.

Abstract: The information processing apparatus includes: a process unit having one or more registers that retain data used for calculation; a compression unit that compresses and saves the content in the register to a stack memory; and a decompression unit that decompresses and restores the data saved in the stack memory, to the corresponding registers. If a first decoding unit included in the process unit has decoded a call instruction which is assigned a compression control bit, the compression unit, in executing the call instruction, performs compression before saving the content of the registers to the stack memory. If a second decoding unit included in the process unit has decoded a return instruction which is assigned a decompression control bit, the decompression unit, in executing the return instruction, performs decompression before restoring the content saved in the stack memory to the registers.

Abstract: A system, device, and method for managing file security attributes in a computer file storage system generates a set of Windows file security attributes from a set of UNIX file security attributes. The set of Windows file security attributes includes a UNIX-specific SID for a UNIX name that could not be translated into a Windows name. The set of Windows file security attributes also includes a set of Windows file permissions derived from a set of UNIX file permissions.

Abstract: An I/O controller having separate command and data paths, thereby eliminating the bandwidth used by the commands and thus increasing bandwidth available to the data buses. Additionally, the I/O controller uses multiple dedicated data paths, for example, dedicated distributed buses, and provides increased speed due to improved hardware integration. The I/O controller employs distributed processing methods that decouple the external microprocessor from much of the decision-making, thereby providing improved operating efficiency and thus more useable bandwidth at any given clock frequency. Accordingly, the I/O controller is capable of maximizing I/O operations (IOPS) on all I/O ports by functioning at the rate of I/O connections to hosts and storage elements without becoming a bottleneck.

Abstract: A multi-threaded processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the first instruction fetch unit and the second instruction fetch unit. An execution unit, which executes a first active thread and a second active thread is coupled to the scheduler unit. The multi-threading processor also includes a register file coupled to the execution unit. The register file switches one of the first active thread and the second active threads with a first inactive thread.

Abstract: A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor (12) can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified bit of a register (80, 78, 76b) being set or cleared and which specifies which bit of the specified register to use as a branch control bit.

Abstract: A processor has a central processing unit and a first interface. The central processing unit sets a communication parameter in a configuration register in the communication interface. A direct memory access controller or a data transfer controller then sets the same parameter in a register in a communication setup interface or an output port controller, which transmits the parameter to an external device with which the processor communicates through the communication interface. Alternately, the central processing unit sets the communication parameter in the communication setup interface or output port controller, and the direct memory access controller or data transfer controller sets the same parameters in the configuration register in the communication interface. Either scheme reduces the load on the central processing unit.

Abstract: A method for optimizing a register file hierarchy in a multithreaded processor. The method includes providing a register file hierarchy with a plurality of register file cells, associating the plurality of register file cells with respective threads when the processor is operating in a multithreaded mode and flattening the plurality of register file cells with a single thread when the processor is operating in a single threaded mode. The register file cells correspond to threads of the multithreaded processor.

Abstract: A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for receiving an input data value tagged with a data validity tag and an output for outputting an intermediate result tagged with a data validity tag. The data validity tags indicate the validity of the data. Before a loop is executed, the data validity tags are set to indicate that the associated data values are invalid. During execution of the loop body a functional unit checks the validity of input data. If all of the input data values are valid the functional operation is performed, the corresponding data validity tag set to indicate that the result is valid. If any of the input data values is invalid, the data validity tag of the result is set to indicate that the result is invalid. To eliminate the epilog, an iteration counter is associated with each sink unit of the vector processor.

Abstract: A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

Abstract: When the destinations of local electrical signals are local computers, the local electrical signals are transmitted to the corresponding destination local computers via the keyboard video mouse (KVM) switch directly. When the destinations of the local electrical signals are remote computers, at least one network packet having multiple data sections for correspondingly storing the local electrical signals is generated by the current KVM switch referring to the local electrical signals. A communication is established among a plurality of the KVM switches using a network protocol, for communicating the network packets thereof. At least one remote electrical signal is obtained from another network packet transmitted by another KVM switch, and then is transmitted to the corresponding destination local computer.

Abstract: A boot menu is provided for manual setting of serial port parameters. A serial console mode menu allows an operator to set serial port parameter values. After the user selects the serial port parameters, when the controller continues with the boot process, the serial port is initialized with the newly selected parameters. A mechanism is also provided for manual setting of serial port parameters through an administrative management window at the host. In addition, an adaptive baud rate negotiation mechanism using the Universal Asynchronous Receiver Transmitter (UART) registers in the serial port is provided. The adaptive baud rate negotiation is based on the return characters received from a break character from the serial console. The mechanism uses a look-up table for the baud rate versus the bit pattern that is received. The mechanism then sets the baud rate based on the look-up table values.

Abstract: A processor having a plurality of processing elements and a decoder operable to decode an instruction. Each of the plurality of processing elements includes: a transfer pattern storage unit operable to store a transfer pattern value that indicates a processing element from which data is transferred; a transfer unit operable to perform a data transfer from the processing element indicated by the transfer pattern value; and an update unit operable to update the transfer pattern value stored in the transfer pattern storage unit, in accordance with a result of decoding a latest instruction by the decoder.