Abstract: A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.

Abstract: A multiprocessor data processing system is described wherein the processors communicate to each other via a shared memory. Each of the processors comprises an administration unit (18a) and a computational unit. The administration unit of a writing processor maintains information defining a section in the memory which is free for storing data objects for readout by the reading processor. The administration unit of the reading processor maintains information defining a section in the memory in which the writing processor has written completed data for the data objects. The processors are arranged to signal a message to another processor via a processor synchronization channel for updating the information in the administration unit of said other processor.

Abstract: The present invention is generally directed to a method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage data transfers between processor registers that are configured to emulate a top portion of a stack and memory, which contains, the remainder of the stack. Some embodiments utilize a variable buffer that is configured to buffer transfers between the processor registers and the memory. The actual amount of data stored in the variable buffer is configured to be flexible, so that transfers between the variable buffer and processor registers are managed to keep the processor registers filled with active stack data (assuming that stack data exists). However, transfers between the variable buffer and memory may be configured to occur only when the variable buffer exceeds certain fill capacities.