Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.

Abstract: In some examples, a system partitions a shared memory address space of a shared memory among a plurality of processing entities into a plurality of memory partitions, where a respective memory partition is associated with a respective processing entity. A first processing entity forwards, to a second processing entity, a first data operation, based on a determination by the first processing entity that the first data operation is to be applied to data for a memory partition associated with the second processing entity. The second processing entity applies the first data operation that includes writing data of the first data operation to the memory partition associated with the second processing entity using a non-atomic operation.

Abstract: A memory controller, a method of operating the memory controller, and an electronic device including the memory controller are disclosed. The method of operating a memory controller, comprising receiving, from a host core, a plurality of commands for a memory, identifying, from among the plurality of commands, processing in memory (PIM) commands to execute one or more operations in the memory, verifying ordering information from a data field in each of the PIM commands, and reordering the PIM commands based on the ordering information and transmitting the reordered PIM commands to the memory.

Abstract: The data processing apparatus includes a memory protection setting storage unit capable of storing a plurality of address sections as memory protection setting targets, a plurality of first determination units provided for each of the address sections stored in the memory protection setting storage unit and provisionally determining whether or not an access request is permitted based on whether or not an access destination address specified by the access request corresponds to the address section acquired from the memory protection setting storage unit, and a second determination unit finally determining whether or not the access request is permitted based on the classification information and the results of provisional determinations by the first determination unit.

Abstract: The present technology relates to an electronic system including a host and a memory system. The host includes a request merge manager configured to generate one or more operation request sets, a first request set queue configured to store one or more of transmission request sets and operation request sets, a first scheduler configured to control the priorities of the operation request sets and the transmission request sets, a second request set queue configured to store the operation request sets sequentially output from the first request set queue, a second scheduler configured to generate a transmission request set, and a request set detector configured to transmit, to the first scheduler, request information on a request set having a highest priority.

Abstract: Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.

Abstract: A method includes, responsive to a SET command associated with a key-value store, concurrently updating the key-value store maintained on a non-persistent memory device of a memory sub-system and a mirror of the key-value store maintained on a persistent memory device of the memory sub-system. The method further includes responsive to a GET command associated with the key-value store, retrieving a value of a key from the key-value store maintained on the non-persistent memory device.

Abstract: According to one embodiment, a computational storage device comprises a nonvolatile memory and a controller configured to control a data process including a first process and a second process. The first process writes data, designated by a first command received from an external device, to the nonvolatile memory. The second process reads data, designated by a second command received from the external device, from the nonvolatile memory and transmits read data to the external device. The controller comprises a processor configured to determine whether to perform the data process in accordance with information included in the first or second command.

Abstract: Generally discussed herein are devices, systems, and methods for software memory tagging that provides buffer overflow protection. A method can include responsive to a memory write operation to write data to a heap of a memory, identifying a first tag value associated with a first address of the memory write operation in the bit map, comparing, for each address after the first address affected by the memory write operation, respective tag values in a bit map of the memory to the identified first tag value, and halting execution of the application if any of the respective tag values do not match the first tag value.

Abstract: A method including, responsive to receiving a request identifying a volume and indicating a command to take a snapshot of the volume, mapping a second logical grouping of data to reference the first logical grouping of data, and remapping the first volume to map to the second logical grouping of data instead of the first logical grouping of data such that the first volume remains addressable with similar access permissions before and after creating the snapshot. The method also includes, in response to receiving a write request targeting the second logical grouping, splitting the second logical grouping into a plurality of ranges including a first range and a second range; wherein the first range of the second logical grouping maps to the first logical grouping, and the write request is performed on the second range of the second logical grouping.

Abstract: The present invention provides a storage device including a controller and methods for operating the storage device and the controller. A controller of a storage device may comprise: an interface controller; a memory controller; a processor configured to transmit downstream commands and upstream commands to the memory controller. The memory controller may be coupled between the interface controller and the processor and may comprise: a first command queue; a second command queue; and a tag generator. The memory controller may be configured to: store a first command received from the processor in the first command queue; store a second command received from the processor in the second command queue; and in response to a first access region of the first command overlapping a second access region of the second command in the second queue, assign an order tag to the second command based on a first serial number of the first command by the tag generator.

Abstract: According to one embodiment, in response to receiving a first namespace create command specifying a first attribution from a host, a controller creates a first namespace having the first attribution and a first logical address range. The first logical address range includes logical addresses. The controller sets each of the logical addresses to an unallocated state in which a physical address of the nonvolatile memory is not mapped, during a first period from a time when receiving a power loss advance notification or when detecting an unexpected power loss until a time when the controller becomes a ready state by resupply of a power to the memory system.

Abstract: An electronic device includes a temporary memory, a non-volatile memory and a processor. The temporary memory includes at least one secure region. The non-volatile memory is configured to store at least one higher-level secure program and a plurality of commands. The processor is connected to the temporary memory and the non-volatile memory for executing the plurality of commands to: when receiving a wake-up command, initialize the at least one secure region; and through the at least one higher-level secure program, recover the at least one secure region, or decrypt encrypted data stored in the non-volatile memory to recover the at least one secure region. In addition, a hibernation recovery method is also disclosed herein.

Abstract: A storage device includes a memory die; a storage controller processor configured to control an operation performed in the memory die by scheduling a plurality of commands provided to the memory die; and memory storing a command queue corresponding to the memory die, wherein the storage controller processor is configured to, receive the plurality of commands respectively from a first tenant and a second tenant; schedule the plurality of commands in the command queue, according to the first and second tenants providing the plurality of commands; and reschedule the plurality of commands according to the operation performed in the memory die and urgency of the plurality of commands, and control the memory die to process the plurality of commands in an order different from an order in which the plurality of commands were received by the storage controller processor.

Abstract: Methods, apparatus and systems for adaptive fabric allocation for local and remote emerging memories-based prediction schemes. In conjunction with performing memory transfers between a compute host and memory device connected via one or more interconnect segments, memory read and write traffic is monitored for at least one interconnect segment having reconfigurable upstream lanes and downstream lanes. Predictions of expected read and write bandwidths for the at least one interconnect segment are then made. Based on the expected read and write bandwidths, the upstream lanes and downstream lanes are dynamically reconfigured. The interconnect segments include interconnect links such as Compute Exchange Link (CXL) flex buses and memory channels for local memory implementations, and fabric links for remote memory implementations. For local memory, management messages may be used to provide telemetry information containing the expected read and write bandwidths.

Abstract: An intercept engine is installed on a computer and includes an intercept filter adapted to intercept selected commands transmitted between a file system and a storage device. The intercept engine also includes an intercept manager adapted to transmit to the intercept filter one or more primitives, wherein each primitive includes device information specifying a device, wherein a command directed to the specified device is to be intercepted, command type information specifying a type of command to be intercepted, and follow-up action information specifying an action to be performed after the command has been intercepted. A primitive may also include default action information specifying an action to be performed with respect to the command if a communication between the intercept filter and the intercept manager is interrupted. The intercept engine intercepts commands transmitted between the file system and the storage device in accordance with the one or more primitives.

Abstract: A first block that is assigned a first sequence identifier can be identified. A determination can be made as to whether the assigned first sequence identifier satisfies a threshold sequence identifier condition that corresponds to a difference between the first sequence identifier assigned to the first block and second sequence identifier assigned to a second block. In response to determining that the assigned first sequence identifier satisfies the threshold sequence identifier condition, a media management operation can be performed on the first block.

Abstract: A storage device includes a first physical space including first nonvolatile memory devices, a second physical space including second nonvolatile memory devices physically isolated from the first nonvolatile memory devices, and a storage controller that fetches a command from an external device and performs an operation corresponding to the command in any one of the first and second physical spaces, based on information included in the fetched command.

Abstract: The present disclosure includes apparatuses and methods related to performing background operations in memory. A memory device can be configured to perform background operations while another memory device in a memory system and/or on a common memory module is busy performing commands received from a host coupled to the memory system and/or common memory module. An example apparatus can include a first memory device, wherein the first memory device can include an array of memory cells and a controller configured to perform a background operation on the first memory device in response to detecting a command from a host to a second memory device.

Abstract: Disclosed is a data cache or data management device for caching data between at least one processor and at least one memory, and supporting an artificial neural network (ANN) operation executed by the at least one processor. The data cache device or the data management device can comprise an internal controller for predicting the next data operation request on the basis of ANN data locality of the ANN operation. The internal controller monitors data operation requests associated with the ANN operation from among data operation requests actually made between the at least one processor and the at least one memory, thereby extracting the ANN data locality of the ANN operation.