Abstract: Techniques for managing memory involve: determining a set of weights corresponding to a plurality of command queues in the memory, each weight indicating the number of commands allowed to be transmitted in a corresponding command queue; detecting whether a transmission delay occurs in the plurality of command queues; and adjusting the set of weights based on a result of the detection. Accordingly, transmission and processing efficiencies of commands in a command queue can be improved, and transmission bandwidth can be used more efficiently.

Abstract: An apparatus for operating an input/output (I/O) interface in a virtual machine is provided. The apparatus is configured to: map a first portion of a memory device to a configuration space of an I/O interface; obtain a first mapping table that maps a set of host space virtual addresses to a first set of physical addresses associated with the first portion of the memory device; obtain a second mapping table that maps a second set of physical addresses associated with a second portion of the memory device accessible by a virtual machine to the set of host space virtual addresses; generate a third mapping table that maps the second set of physical addresses to the first set of physical addresses; and provide the third mapping table to a device driver operating in the virtual machine, to enable the device driver to access the configuration space of the I/O interface.

Abstract: A first block that is assigned a first sequence identifier can be identified. A determination can be made as to whether the assigned first sequence identifier satisfies a threshold sequence identifier condition that corresponds to a difference between the first sequence identifier assigned to the first block and second sequence identifier assigned to a second block. In response to determining that the assigned first sequence identifier satisfies the threshold sequence identifier condition, a media management operation can be performed on the first block.

Abstract: A memory system including a history buffer, a hash calculator, a read pointer table, a history buffer writing circuit, a read pointer writing circuit, a read pointer reading circuit, a history buffer reading circuit, a matching circuit replacing the input data string with a reference information referring the matching candidate data string in the case where at least a part of the input data string and a part of the matching candidate data string match. Reading of the read pointer by the read pointer reading circuit and reading of the stored input data string by the history buffer reading circuit are executed after writing of the read pointer by the read pointer writing circuit and writing of the input data string by the history buffer writing circuit are finished.

Abstract: Techniques involve detecting whether a transaction of modifying configuration data of a storage system is initiated, the configuration data being stored in a database and a buffered version being stored in memory independent of the database. The techniques further involve in accordance with detection that the transaction is initiated, building a data buffer to buffer a section to be modified, the data buffer being mapped to a storage sector of the memory in which the section is expected to be stored. The techniques further involve determining whether the transaction successfully completed and in accordance with a determination that the transaction fails to successfully complete, releasing the data buffer and aborting the transaction, without modifying the buffered version. Accordingly, the configuration data in the memory remains as the previous version and are not modified before the transaction is successfully completed, which makes it possible to abort the transaction.

Abstract: In a magnetic recording drive that includes a shingled magnetic recording (SMR) region and a conventional magnetic recording (CMR) region, the quantity of validation data that is stored by the CMR region is reduced. In the magnetic recording drive, verification data stored in the CMR region is invalidated under certain circumstances, including when an SMR band is closed, when an SMR band is indicated by a host to be reused, when an SMR band is indicated to be finished, and when a last data track of an SMR has data stored therein.

Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage devices, for data processing and storage. One of the methods includes maintaining, by a storage system, a data log file in a source storage device of the storage system. The storage system identifies one or more characteristics of the data log file and one or more characteristics of the source storage device, and determines a migration metric of the data log file based on the one or more characteristics of the data log file and the one or more characteristics of the source storage device. The storage system determines whether to migrate the data log file according to the migration metric. In response to determining to migrate the data log file, the storage system migrates the data log file from a source location in the source storage device to a destination storage device.

Abstract: Techniques in electronic systems, such as in systems including a processing chip and one or more external memory chips, provide improvements in one or more of system security, performance, cost, and efficiency. The processing chip includes autonomous hardware that enables the processing chip, without a use of any CPUs, to form an association between itself and a particular flash chip. Prior to an initial operational use of the processing chip, the autonomous hardware is able to generate a key unique to the processing chip using a physically unclonable function, and then to form the association by encrypting a stream of data using the key and writing the encrypted result to the flash chip. For example, the stream of data comprises a bootloader and an operating system, and the processing chip is able to begin the initial operational use by securely booting using data copied from the flash chip.

Abstract: A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.

Abstract: An apparatus comprises memory access circuitry to perform a tag-guarded memory access in response to a target address, the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target address. The memory access circuitry is responsive to a sequence of received target addresses specifying a sequence of addressed locations to perform a non-tag-guarded memory access that does not perform the guard-tag check to a subset of the sequence of addressed locations.

Abstract: Memory prefetching in a processor comprises: identifying, in response to memory access instructions, a pattern of addresses; in response to a first memory access request corresponding to a sub-pattern of the pattern of addresses, prefetching a first address that is offset from the sub-pattern of addresses by a first lookahead value, wherein the first address is part of the pattern; measuring a memory access latency; determining, based on the memory access latency, a second lookahead value, wherein the second lookahead value is different from the first lookahead value; and in response to a second memory access request corresponding to the sub-pattern of the pattern of addresses, prefetching a second address, wherein the second address is part of the pattern, and wherein the second address is offset from the sub-pattern of addresses by the second lookahead value.

Abstract: A data storage device utilized for accessing boot data includes a flash memory, a controller and a RAM. The flash memory includes several blocks, and each block includes several pages. The controller is coupled to the flash memory and the RAM. The controller receives a write command from a host and determines whether the data of the write command is system data or normal data. If the data to be written is system data, the controller transmits a confirm message to the host after the system data has been completely stored on the data storage device.

Abstract: A method for data management is provided. The method comprises: storing the plurality of items in a contiguous space within the memory, executing an instruction containing an address and a size that together identify the contiguous space to transmit the plurality of items from the main memory to a random-access memory (RAM) on a chip, and the chip includes a computing unit comprising a plurality of multipliers; and instructing the computing unit on the chip to: retrieve multiple of the plurality of items from the RAM; and perform a plurality of parallel operations using the plurality of multipliers with the multiple items to yield output data.

Abstract: According to embodiments of the present disclosure, there is provided a data transmission apparatus. The data transmission apparatus includes a plurality of first ports, a plurality of second ports, and a plurality of data channels. The plurality of first ports are coupled to a processing unit. The plurality of second ports are coupled to a plurality of memories. The plurality of data channels are disposed among the first ports and the second ports to form an interleaving network having a plurality of layers, and configured to transmit data among the processing unit and the plurality of memories, such that each layer in the interleaving network includes at least one interleaving sub-network.

Abstract: A method can be used to determine an overall memory size of a global memory area to be allocated in a memory intended to store input data and output data from each layer of a neural network. An elementary memory size of an elementary memory area intended to store the input data and the output data from the layer is determined for each layer. The elementary memory size is in the range between a memory size for the input data or output data from the layer and a size equal to the sum of the memory size for the input data and the memory size for the output data from the layer. The overall memory size is determined based on the elementary memory sizes associated with the layers. The global memory area contains all the elementary memory areas.

Abstract: The technology disclosed herein pertains to a method for determining expected command completion time (CCT), the method including receiving a plurality of position error signals (PESs) for an HDD over a predetermined time period, determining sigma of the plurality of PESs, retrieving upper off-track limits (UOL) for one or more data sectors of the HDD, calculating average number of retrieved sectors (A) between two consecutive occurrences of the |PES|>UOL for the HDD, and determining required number of revolutions (CCT) to collect data based on the average number of retrieved data sectors (A) and a total number of requested data sectors (N).

Abstract: A storage device includes at least one non-volatile memory device, a memory controller encrypting data using key information, storing the encrypted data in the at least one non-volatile memory device, or reading the encrypted data from the at least one non-volatile memory device, decrypting the read encrypted data using the key information and outputting the decrypted data to an external device, and a security chip connected to the memory controller, and storing the key information, and including an identification module for use in a data disposal operation.

Abstract: A storage device includes a first physical space including first nonvolatile memory devices, a second physical space including second nonvolatile memory devices physically isolated from the first nonvolatile memory devices, and a storage controller that fetches a command from an external device and performs an operation corresponding to the command in any one of the first and second physical spaces, based on information included in the fetched command.

Abstract: A logical map represents fragments from separate versions of a data object. Migration of data from a first (old) version to the second (new) version happens gradually, where write operations go to the new version of the data object. The logical map initially points to the old data object, but is updated to point to the portions of the new data object as write operations are performed on the new data object. A background migration copies data from the old data object to the new data object.

Abstract: A memory system, a memory controller and an operating method are disclosed. By determining, based on status check delay information, a time point at which a status check command is sent to a memory device and updating the status check delay information while the memory device is in an idle state, it is possible to minimize a degradation in the performance of a program operation for the memory device including a plurality of memory dies, and it is possible to reflect a variation in an operation characteristic of the memory device, on the program operation.