Abstract: Systems and methods that may be used to implement overlapping data caching for object application program interfaces (APIs). A unique identifier may be assigned to each sub-component of an object API request. The unique identifiers may be used to determine if sub-components of one object API request overlaps with a sub-component of a prior different request such that a data response for the prior different request can be retrieved from the cache and used as part of the data response for the current object API request.

Abstract: A controller for controlling a memory devices is provided to include: a first core configured to control first memory dies; a second core configured to control second memory dies; and a host interface configured to: receive submission queue tail pointers and command information on each of commands corresponding to the tail pointers from host, classify the commands into a first address command associated with a first logical address and a second address command associated with a second logical address based on the command information, fetch the first and second address commands from host, and provide the first address command to the first core and the second address command to the second core based on the processing order of the first and second address commands determined based on status of the first memory dies and the second memory dies.

Abstract: A method, computer program product, and computer system for identifying, by a computing device, storage containers that contain cold data. At least a portion of the storage containers may be processed to determine whether a first compression technique will result in a higher level of compression above a threshold level of compression than a second compression technique. The storage containers may be processed using the first compression technique based upon, at least in part, determining that the first compression technique will result in the higher level of compression above the threshold level of compression than the second compression technique.

Abstract: A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, the memory system may determine, according to a time period to which the length of the idle time belongs among a plurality of set time periods, a command pattern indicating a command type of a command expected to be received from the host, and may execute an operation corresponding to the command pattern. In this case, the type of command may be a read command, a write command, or an erase command, and the command pattern may be a read pattern, a write pattern, or an erase pattern.

Abstract: A method comprises receiving a message comprising an identifier for an address template, using the identifier to select the address template from a set of address templates, determining a set of memory addresses for a corresponding set of memory operations using the address template, and executing the memory operations.

Abstract: A system includes dice and a processing device operatively coupled to the dice. The processing device to perform operations including: storing data of one or more stripes at a first group of dice; determining that the first group of dice has satisfied an endurance condition threshold comprising a predetermined number of write operations or bit errors; changing the endurance condition threshold to a changed endurance condition threshold, wherein the changed endurance condition threshold is based on a number of the first group of dice to come within a threshold percentage of satisfying the endurance condition threshold; and using the changed endurance condition threshold to determine a time to store data of one or more subsequent stripes at a second group of dice, wherein the second group of dice includes at least one die that is not included in the first group of dice.

Abstract: Embodiments of the present disclosure relate to an UFS device and an operating method thereof. According to the embodiments of the present disclosure, the UFS device may collect status information of the UFS device, create an Acknowledgement and Flow Control (AFC) frame including the collected status information, and transmit the AFC frame to a host performing communication with the UFS device.

Abstract: A method for maintaining an availability of a storage system, the method may include obtaining, by a control module of the storage system, problem related information generated by one or more compute nodes of the storage system, the problem related information is indicative of one or more problems associated with an execution of one or more storage operations; determining, by the control module and based on the problem related information, whether to forbid an execution of a storage operation of the one of more storage operations; and updating, by the control module, and based on the determining, a forbidden storage operation data structure that is accessible to the compute nodes of the storage system.

Abstract: A method for cache coherency in a reconfigurable cache architecture is provided. The method includes receiving a memory access command, wherein the memory access command includes at least an address of a memory to access; determining at least one access parameter based on the memory access command; and determining a target cache bin for serving the memory access command based in part on the at least one access parameter and the address.

Abstract: Methods, systems, and devices for status information retrieval for a memory device are described. In some examples, a memory device may include a set of status registers, each of which may be configured to store a corresponding set of status information. For example, at least some of the status registers may store status information for a corresponding portion of the memory device. The memory device may receive a command to output status information along with an indication of one or more particular status registers from which to output status information in response to the command. In response to the command and indication, the memory device may output status information from any quantity of status registers, including any type of status information, in a single stream or burst.

Abstract: A technique for scheduling access to a resource arranges tasks into multiple classes, where each class has a respective share and a respective priority. The share of a class sets an amount of access allocated to the class, and the priority sets an order in which the class can use its share, with higher priority classes getting access before lower-priority classes. The technique assigns latency-critical tasks, such as synchronous I/O tasks, to a first class having the highest priority and assigns bandwidth-critical tasks, such as background I/O processing, to a second class having a lower priority.

Abstract: The present disclosure includes apparatuses and methods related to memory alignment. An example method comprises performing an alignment operation on a first byte-based memory element and a second byte-based memory element such that a padding bit of the first byte-based memory element is logically adjacent to a padding bit of the second byte-based memory element and a data bit of the first byte-based memory element is logically adjacent to a data bit of the second byte-based memory element.

Abstract: A method for performing a sudden power-off recovery operation of a controller controlling a memory device, the method includes: obtaining open block information for open blocks of the memory device and read counts for the open blocks; updating each of the read counts by adding a set value to each of the read counts; storing the updated read counts in the memory device; sequentially reading pages in each of the open blocks without updating the read counts for the open blocks, based on the open block information, to detect a boundary page after the storing of the updated read counts in the memory device; and controlling the memory device to program dummy data in the detected boundary page.

Abstract: A data processing system is provided to include a memory system to store data and information; and a host in communication with the memory system and including a submission queue for queueing a command to be processed by the memory system, the host configured to provide the memory system with a submission queue tail pointer indicating a tail of the submission queue and command information on a command, wherein the memory system is configured to receive command information on the command, performs a pre-operation on the command based on the command information, and fetches the command from the submission queue based on a result of the pre-operation.

Abstract: Systems and method for providing tier selection for data based on a weighted flash fragmentation factor. A weighted flash fragmentation factor is determined indicating a severity of fragmentation in a non-volatile storage based on a logical block address range in a logical-to-physical mapping table for data from a host device to be stored in the tiered data storage system. The factor is shared with the host device to determine a tier selection. The data is stored according to the tier selection based on the factor.

Abstract: A memory system includes a memory device comprising a plurality of pages, and a controller suitable for storing data, inputted in response to a write command received from a host, in corresponding pages among the plurality of pages, wherein the controller generates and manages a bitmap table indicating order information of the inputted data according to the type of the write command.

Abstract: A memory subsystem for use with a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units configured for processing one or more workgroups each comprising a plurality of SIMD tasks, the memory subsystem comprising: a shared memory partitioned into a plurality of memory portions for allocation to tasks that are to be processed by the processor; and a resource allocator configured to, in response to receiving a memory resource request for first memory resources in respect of a first-received task of a workgroup, allocate to the workgroup a block of memory portions sufficient in size for each task of the workgroup to receive memory resources in the block equivalent to the first memory resources.

Abstract: A memory address generator for generating an address of a location in a memory includes a first address input for receiving a first address having a location in the memory being accessed during a first memory access cycle, and a next address output configured to output a next address comprising a location in the memory to be accessed during a subsequent memory access cycle based on the current address and a memory address increment value The address increment unit includes a counter arrangement and a selector arrangement, wherein each counter of the counter arrangement is configured to provide an output signal at the output indicative of a maximum value being reached and the selector arrangement is configured to provide a candidate memory address increment value based on the output of the counter arrangement as the memory address increment value output by the address increment unit.

Abstract: The present disclosure generally relates to searching an overlap table for data requested to be read in a plurality of read commands received. Rather than searching the table for data corresponding to each command individually, the searching occurs for the plurality of commands in parallel. Furthermore, the overlap table can comprise multiple data entries for each line. The number of read commands can be accumulated prior to searching, with the accumulating being a function of a queue depth permitted by the host device. Parallel searching of the overlap table reduces the average search time.