Abstract: Methods for controlling a ramp rate of an output voltage derived from one or more charge pumps and reducing variation in the ramp rate due to process, voltage, and temperature (PVT) variations are described. In some embodiments, the ramp rate of the output voltage from one or more charge pumps may be controlled using a ramp rate control circuit that uses a digital counter to adjust (or step up) the output voltage from the one or more charge pumps based on a ramp rate schedule. The ramp rate schedule may specify varying output voltage levels for the one or more charge pumps during a time period in which the output voltage charges up from a first voltage to a second voltage greater than the first voltage.

Abstract: The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.

Abstract: Magnetic memory devices having an antiferromagnetic reference layer based on Co and Ir are provided. In one aspect, a magnetic memory device includes a reference magnetic layer having multiple Co-containing layers oriented in a stack, wherein adjacent Co-containing layers in the stack are separated by an Ir-containing layer such that the adjacent Co-containing layers in the stack are anti-parallel coupled by the Ir-containing layer therebetween; and a free magnetic layer separated from the reference magnetic layer by a barrier layer. A method of writing data to a magnetic random access memory device having at least one of the present magnetic memory cells is also provided.

Abstract: Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. The logic component can include combinational or sequential logic.

Abstract: Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

Abstract: The present patent application describes 9T, 8T, and 7T versions of bitcells used with 1R1W memories. It also describes 9T, 8T, and 7T versions of bitcells used with single port SRAM memories. Different circuits are discussed to support different bitcells and architectures mentioned above. Our 1R1W and single port bitcells and architectures give significant advantages over the conventional bitcells and architectures.

Abstract: An electronic device including an inverter includes a pull-up driving unit configured to drive an output node with a high voltage in response to an input signal; a path switching unit coupled in a path between the pull-up driving unit and the output node according to a direction of a first current flowing between the pull-up driving unit and the output node and operable to selectively switch on or off the path; a pull-down driving unit coupled to the output node to supply a low voltage in response to the input signal; a path blocking unit coupled in a path between the pull-down driving unit and the output node to block the path; and a bypass unit coupled to form a bypass path between the pull-down driving unit and the output node.

Abstract: A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.

Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.

Abstract: A method for determining an optimal voltage pulse for programming a flash memory cell, the optimal voltage pulse being defined by a voltage ramp from a non-zero initial voltage level during a programming duration, wherein the method takes into account a set of parameters including a programming window target value and a drain current target value of the memory cell.

Abstract: A nonvolatile memory device may include a nonvolatile memory cell and a sensing circuit. The sensing circuit is coupled to a bit line of the nonvolatile memory cell. The sensing circuit may be realized using an inverter comprised of a P-channel transistor coupled to a supply voltage line and an N-channel transistor coupled to a ground voltage. The gate of the P-channel transistor is coupled to the ground voltage.

Abstract: A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. The read sensing method includes following steps. Firstly, the plural bit lines are precharged to a precharge voltage. Then, a selected memory cell of the memory array is determined, wherein the selected memory cell is connected with a first bit line of the plural bit lines. Then, the bit line corresponding to the selected memory cell is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to a result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated.

Abstract: A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.

Abstract: Self-referenced magnetic random access memory (MRAM) cell including a magnetic tunnel junction including a sense layer; a storage layer having a storage magnetization; a tunnel barrier layer between the sense and the storage layers; and an antiferromagnetic layer exchange-coupling the storage layer such that the storage magnetization can be pinned when the antiferromagnetic layer is below a critical temperature and freely varied when the antiferromagnetic layer is heated at or above the critical temperature. The sense layer includes a first sense layer having a first sense magnetization, a second sense layer having a second sense magnetization and spacer layer between the first and second sense layers. The MRAM cell can be read with low power consumption.

Abstract: A resistive switching memory device can include three or more electrodes interfacing a switching layer, including a top electrode, a bottom electrode, and a side electrode. The top and bottom electrodes can be used for forming conductive filaments and for reading the memory device. The side electrode can be used to control the resistance state of the switching layer.

Abstract: The disclosed embodiments comprise a flash memory device that can be configured to operate as a read only memory device. In some embodiments, the flash memory device can be configured into a flash memory portion and a read only memory portion.

Abstract: A memory cell includes a first select transistor, a first following gate transistor, an antifuse transistor, a second following gate transistor, and a second select transistor. The first select transistor has a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line. The first following gate transistor has a first terminal coupled to the second terminal of the first select transistor, a second terminal, and a gate terminal coupled to a following control line. The antifuse transistor has a first terminal coupled to the second terminal of the first following gate, and a gate terminal coupled to an antifuse control line. The second following gate transistor and the second select transistor are disposed symmetrically to the first following gate transistor and the second select transistor with respect to the antifuse transistor.

Abstract: A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value.

Abstract: A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.

Abstract: A circuit utilizing memcapacitive elements for mixed memory storage and polymorphic computing is introduced. The circuit includes a plurality of memory cells each selectively or fixedly connected to a word line, bit line and dual bit line. Each memory cell includes a memcapacitive element. Voltage pulse generators can selectively applying voltage pulses to the memory cells. A method for mixed memory storage and polymorphic computing in at least two memory cells is provided. Data is stored by selectively applying voltage pulses to an individual memory cell to set an internal charge level of the memcapacitive element. Logic functions are conducted by applying voltage pulses having independent amplitudes to at least two memory cells to achieve internal charges in the memcapacitive elements of the cells to store an output bit according to a logic map that depends upon applied independent voltage pulse amplitudes.