Patents Examined by Tri Hoang
  • Semiconductor memory device and operation method thereof
    Patent number: 9396818
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells and a plurality of redundancy memory cells, a fuse array to be programmed with information of a defective memory cell among the memory cells of the memory cell array, and a control unit suitable for setting up a program operation section for programming the fuse array in response to an external command, wherein when the control unit sets up the program operation section, the control unit sets up a refresh operation section for refreshing the memory cell array, which is terminated before the program operation section ends without overlapping with the program operation section.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: July 19, 2016
    Assignee: SK Hynix Inc.
    Inventor: Choung-Ki Song
  • Multi-supply dual port register file
    Patent number: 9396790
    Abstract: A multi-supply dual port register file is disclosed. The register file may be used for transferring data between two power domains that operate on different voltages or frequencies. The register file comprises a memory cell that stores the data transferred between the domains. The memory cell may be independently supplied by a reference voltage independent of that of the memory periphery. A write power domain write data to the memory cell in accordance with its operating voltage and frequency and an independent read power domain may read data from the memory cell in accordance with its independent operating voltage and frequency. The register file facilitates efficient crossing between the read and write power domains.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: July 19, 2016
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Amit Chhabra, Kailash Digari
  • Electronic device and method for operating the same
    Patent number: 9384828
    Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a plurality of variable resistance elements; a plurality of read voltage application terminals configured to supply different levels of read voltages to respective one ends of the plurality of variable resistance elements; and an analog-to-digital conversion unit configured to generate multi-bit digital data corresponding to a total current which is acquired by summing currents flowing through the plurality of variable resistance elements.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: July 5, 2016
    Assignee: SK hynix Inc.
    Inventor: Byoung-Chan Oh
  • Non-volatile static random access memory circuits
    Patent number: 9378807
    Abstract: A non-volatile static random access memory (nvSRAM) circuit is provided. The nvSRAM circuit includes first and second switches and a latch circuit. The first switch has a first terminal coupled to a first bit line. The second switch has a first terminal coupled to a second bit line. The latch circuit is coupled to second terminals of the first and second switches. The latch circuit has a first non-volatile memory element. When the nvSRAM circuit is at a writing mode, first input data on the first bit line is written into in the latch circuit, and the first non-volatile memory element has a first state corresponding to the first data. When the nvSRAM circuit is at a reading mode, first readout data is generated according to the first state of the first non-volatile memory element is generated and provided to the first bit line.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: June 28, 2016
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Young Tae Kim, Ming-Huei Shieh
  • Semiconductor device, electronic component, and electronic device
    Patent number: 9378776
    Abstract: A semiconductor device with a small cell area and excellent data read/write capability is achieved. In the semiconductor device, a wiring for writing data is provided, and a first transistor with a low off-state current is turned on to supply data to a gate of a second transistor and is turned off so that electric charge corresponding to data is retained. Moreover, a wiring for reading data is provided, and a third transistor is turned on so that data is read out in accordance with the on/off state of the second transistor retaining the electric charge. With this configuration, data write and data read are achieved in the same cycle.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: June 28, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Electronic device and method for operating the same
    Patent number: 9378819
    Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a cell array divided into at least two regions each of which includes a plurality of memory cells each including a transistor and a resistance variable element; a write driver circuit configured to supply write current to a memory cell selected among memory cells in the cell array; and a back bias voltage supply unit configured to supply back bias voltages with different levels to the regions in the cell array.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: June 28, 2016
    Assignee: SK hynix Inc.
    Inventor: Yeon-Hee Park
  • Reference column of semiconductor memory, and electronic device including the same
    Patent number: 9373394
    Abstract: A reference column of a semiconductor memory includes a reference bit line; a reference source line; and first to Nth resistive memory cells disposed between the reference bit line and the reference source line. Data of a first state is stored in the first resistive memory cell and data of a second state is stored in the Nth resistive memory cell before a read operation, and the first and Nth resistive memory cells form current paths between the reference bit line and the reference source line in the read operation.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: June 21, 2016
    Assignee: SK hynix Inc.
    Inventor: Ji-Wang Lee
  • Memory device
    Patent number: 9368553
    Abstract: According to one embodiment, a memory device includes a first active area, formed on the substrate, which extends in a third direction. The memory device also includes three gate electrodes, provided on the first active area, which extend in a second direction intersecting the third direction. The memory device also includes at least two or more upper-layer interconnects and at least two or more lower-layer interconnects, provided on the first active area, which extend in a first direction intersecting the second direction and the third direction. The memory device also includes first transistors of three, each of them is provided at the intersection point between the first active area and the three gate electrodes. The memory device also includes the first transistors of three are one device isolation transistor and two cell transistors.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: June 14, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Asao
  • Semiconductor memory apparatus
    Patent number: 9368171
    Abstract: A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. The data sensing section may generate a comparison flag signal by comparing an output data outputted from the memory cell with a reference voltage in response to a verification read signal. The programming control section may generate the write signal for an initial write operation and the verification read signal in response to a write command, and generate the write signal for a following write operation as soon as the comparison flag signal is at a predetermined level.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: June 14, 2016
    Assignee: SK HYNIX INC
    Inventors: Chang Yong Ahn, Ho Seok Em
  • Sense amplifier, nonvolatile memory device including the sense amplifier and sensing method of the sense amplifier
    Patent number: 9349428
    Abstract: A sense amplifier, a nonvolatile memory device including the sense amplifier and a sensing method of the sense amplifier are provided. The sense amplifier includes a first comparator that generates a first comparison signal by comparing a first reference signal received from a first reference cell with a sensing target signal received from the selected memory cell, and generates a second comparison signal by comparing the sensing target signal with a second reference signal received from a second reference cell written in different state from the first reference cell, and a second comparator that senses data stored in the selected memory cell by comparing the first comparison signal and the second comparison signal.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: May 24, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Artur Antonyan
  • Erase techniques and circuits therefor for non-volatile memory devices
    Patent number: 9349480
    Abstract: Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: May 24, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Vincenzo Ferragina, Stefano Surico, Giuseppe Moioli, Simone Bartoli
  • Nonvolatile memory device including memory cell array with upper and lower word line groups
    Patent number: 9336887
    Abstract: A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: May 10, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changkyu Seol, Euncheol Kim, Junjin Kong, Hong Rak Son
  • Semiconductor device having compensation capacitor to stabilize power supply voltage
    Patent number: 9337139
    Abstract: Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 10, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Tomohiro Kitano, Hisayuki Nagamine
  • Static random access memory (SRAM) bitcell and memory architecture without a write bitline
    Patent number: 9336861
    Abstract: A bit cell and memory architecture wherein a write bitline is not required is presented. The bitcell and the memory architecture bring a huge improvement in the performance, dynamic power, leakage power, area, and the yield of the memory.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: May 10, 2016
    Assignee: SKAN TECHNOLOGIES CORPORATION
    Inventor: Sudhir S. Moharir
  • Floating gate flash memory device and compilation method thereof
    Patent number: 9337352
    Abstract: The present invention discloses a floating gate flash memory device, comprising: a P-type substrate which has a source and a drain, and a first polysilicon gate, a first control gate and a second polysilicon gate and a second control gate which are respectively located in parallel on the upper and lower sides of the substrate, first and second polysilicon floating gates being respectively provided between the first and second control gates and the substrate; the floating gate flash memory device of the present invention utilizes a double-gate structure, can solve the problems such as the poor programming efficiency of the floating gate flash memory and the high programming current power consumption, by using the compilation mechanism of source side injection.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: May 10, 2016
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventor: Jinglun Gu
  • First-in first-out circuits and methods
    Patent number: 9330740
    Abstract: A first first-in first-out (FIFO) circuit includes a storage circuit, a second first-in first-out (FIFO) circuit, and a third first-in first-out (FIFO) circuit. The storage circuit stores write data at a write address in response to a write clock signal. The storage circuit outputs read data from a read address in response to a read clock signal. A write pointer indicating the write address is synchronized with the write clock signal. A read pointer indicating the read address is synchronized with the read clock signal. The second first-in first-out (FIFO) circuit synchronizes the write pointer with the read clock signal. The third first-in first-out (FIFO) circuit synchronizes the read pointer with the write clock signal.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: May 3, 2016
    Assignee: Altera Corporation
    Inventors: Gregg William Baeckler, David W. Mendel
  • Dynamic selection of output delay in a memory control device
    Patent number: 9330749
    Abstract: In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: May 3, 2016
    Assignee: XILINX, INC.
    Inventors: Dhruv Choksey, Terence J. Magee
  • Systems and methods for trimming control transistors for 3D NAND flash
    Patent number: 9324437
    Abstract: Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: April 26, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuo Pin Chang, Chih-Shen Chang, Hang-Ting Lue
  • Semiconductor memory device
    Patent number: 9324442
    Abstract: A semiconductor memory device includes a memory cell, a sense amplifier electrically connected to the memory cell, the sense amplifier including a node for sensing a voltage during a sense operation and a data latch electrically connected to the node and configured to hold a first voltage corresponding to a voltage of the node when a strobe signal is issued during a strobe operation, and a controller configured to raise the voltage of the node during the strobe operation before the strobe signal is issued.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: April 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Nonvolatile memory and method for improved programming with reduced verify
    Patent number: 9324418
    Abstract: A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: April 26, 2016
    Assignee: SANDISK TECHNOLOGIES, INC.
    Inventors: Yingda Dong, Ken Oowada, Cynthia Hsu